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公开(公告)号：US11764149B2
公开(公告)日：2023-09-19
申请号：US17866782
申请日：2022-07-18
发明人： Suhyun Bark , Kyeongbeom Park , Jongmin Baek , Jangho Lee , Wookyung You , Deokyoung Jung
IPC分类号： H01L21/00 , H01L23/522 , H01L23/528 , H01L27/088
CPC分类号： H01L23/5226 , H01L23/528 , H01L27/088
摘要： A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.
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公开(公告)号：US20220359379A1
公开(公告)日：2022-11-10
申请号：US17866782
申请日：2022-07-18
发明人： Suhyun Bark , Kyeongbeom Park , Jongmin Baek , Jangho Lee , Wookyung You , Deokyoung Jung
IPC分类号： H01L23/522 , H01L23/528 , H01L27/088
摘要： A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.
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3.发明公开公开(公告)号：US20240085812A1
公开(公告)日：2024-03-14
申请号：US18230472
申请日：2023-08-04
发明人： Kyuhee Han , Koungmin Ryu , Kyeongbeom Park , Jongmin Baek , Wookyung You , Woojin Lee , Juhee Lee
IPC分类号： G03F7/00 , G03F7/20 , G03F7/40 , H01L21/033
CPC分类号： G03F7/70925 , G03F7/2004 , G03F7/40 , H01L21/033
摘要： A substrate processing apparatus includes a chamber having an internal space configured to process a substrate loaded therein; a light source configured to emit light on the substrate to harden a photoresist pattern coated on the substrate; and a transparent division part provided between the substrate and the light source, wherein the transparent division part divides the chamber into a first space, in which the light source is provided, and a second space, in which the substrate is provided.
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公开(公告)号：US11424182B2
公开(公告)日：2022-08-23
申请号：US17130293
申请日：2020-12-22
发明人： Suhyun Bark , Kyeongbeom Park , Jongmin Baek , Jangho Lee , Wookyung You , Deokyoung Jung
IPC分类号： H01L21/00 , H01L23/522 , H01L23/528 , H01L27/088
摘要： A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.
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公开(公告)号：US12014980B2
公开(公告)日：2024-06-18
申请号：US18446524
申请日：2023-08-09
发明人： Suhyun Bark , Kyeongbeom Park , Jongmin Baek , Jangho Lee , Wookyung You , Deokyoung Jung
IPC分类号： H01L21/00 , H01L23/522 , H01L23/528 , H01L27/088
CPC分类号： H01L23/5226 , H01L23/528 , H01L27/088
摘要： A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.
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公开(公告)号：US20210391254A1
公开(公告)日：2021-12-16
申请号：US17155126
申请日：2021-01-22
发明人： Wookyung You , Kyeongbeom Park , Sungbin Park , Suhyun Park , Jongmin Baek , Jangho Lee , Seonghun Lim , Deokyoung Jung , Kyuhee Han
IPC分类号： H01L23/522 , H01L23/528
摘要： A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.
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公开(公告)号：US20240030127A1
公开(公告)日：2024-01-25
申请号：US18446524
申请日：2023-08-09
发明人： Suhyun Bark , Kyeongbeom Park , Jongmin Baek , Jangho Lee , Wookyung You , Deokyoung Jung
IPC分类号： H01L23/522 , H01L23/528 , H01L27/088
CPC分类号： H01L23/5226 , H01L23/528 , H01L27/088
摘要： A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.
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公开(公告)号：US11646263B2
公开(公告)日：2023-05-09
申请号：US17155126
申请日：2021-01-22
发明人： Wookyung You , Kyeongbeom Park , Sungbin Park , Suhyun Park , Jongmin Baek , Jangho Lee , Seonghun Lim , Deokyoung Jung , Kyuhee Han
IPC分类号： H01L21/00 , H01L23/522 , H01L23/528
CPC分类号： H01L23/5226 , H01L23/528 , H01L23/5228
摘要： A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.
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公开(公告)号：US20210351123A1
公开(公告)日：2021-11-11
申请号：US17130293
申请日：2020-12-22
发明人： Suhyun Bark , Kyeongbeom Park , Jongmin Baek , Jangho Lee , Wookyung You , Deokyoung Jung
IPC分类号： H01L23/522 , H01L27/088 , H01L23/528
摘要： A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.
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