公开(公告)号：US20190191563A1

公开(公告)日：2019-06-20

申请号：US16103284

申请日：2018-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Min KIM ,  Do-Hyung KIM ,  Kyoung-Sun KIM

IPC: H05K1/11 ,  H05K1/02

Abstract: A printed circuit board (PCB) includes a first insulating layer, a pad disposed on the first insulating layer, and a first reference layer on which the first insulating layer is disposed, the first reference layer including a dielectric passage for forming a return path of a signal that is transmitted to the pad, and a conductive line disposed in the dielectric passage and disposed to form a transmission path of the signal. The PCB further includes a second insulating layer on which the first reference layer is disposed, and a second reference layer on which the second insulating layer is disposed, the second reference layer further forming the return path. A capacitance of the pad corresponds to a distance between the pad and the second reference layer.

公开(公告)号：US20150262620A1

公开(公告)日：2015-09-17

申请号：US14712530

申请日：2015-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Hyung SONG ,  Kyoung-Sun KIM ,  Yong Jin KIM ,  Jae-Jun LEE ,  Sang-Seok KANG ,  Jung-Joon LEE

IPC: G11C5/02

CPC classification number: G11C5/04 ,  G06F13/102 ,  G06F13/4068 ,  G06F13/42 ,  G11C5/02 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/074 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.

Abstract translation: 提供了一种包括印刷电路板的存储器模块; 设置在印刷电路板的一个表面上的第一半导体封装; 以及设置在所述印刷电路板的另一个表面上的第二半导体封装，所述第一半导体封装和所述第二半导体封装具有形成等级的半导体管芯。 由第一半导体封装形成的多个等级由与第二半导体封装形成的等级数不同。 形成相同行列的半导体封装共同接收芯片选择信号，形成其他级别的半导体封装接收不同的芯片选择信号。

公开(公告)号：US20130183839A1

公开(公告)日：2013-07-18

申请号：US13742551

申请日：2013-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Hyun SEOK ,  Kyoung-Sun KIM

IPC: H05K1/11

CPC classification number: H05K1/117 ,  H01L2924/0002 ,  H05K2201/094 ,  H01L2924/00

Abstract: A printed circuit board (PCB) includes a substrate body including a circuit wiring layer; tap terminals provided at a surface of the substrate body and in a peripheral region of the substrate body and electrically connected to the circuit wiring layer; and plating wires corresponding to respective tap terminals, each plating wire extending from an end portion of its respective tap terminal toward an edge of the substrate body and having a line width smaller than a line width of the tap terminal. For at least a first tap terminal, the tap terminal shares an edge with an edge of its respective plating wire. A second tap terminal adjacent the first tap terminal is positioned outside a circle having a radius that equals a length of the plating wire and having a center at a point along the shared edge where the plating wire and first tap terminal connect.

Abstract translation: 印刷电路板（PCB）包括：基板主体，包括电路布线层; 抽头端子，其设置在所述基板主体的表面和所述基板主体的周边区域中，并电连接到所述电路布线层; 以及对应于各个抽头端子的电镀线，每个电镀线从其各个抽头端子的端部朝向衬底主体的边缘延伸并且具有小于抽头端子的线宽的线宽。 对于至少第一抽头端子，抽头端子与其各自电镀线的边缘共享边缘。 与第一抽头端子相邻的第二抽头端子位于具有等于电镀线长度的半径的圆的外侧，并且具有沿着电镀线和第一抽头端子连接的共享边缘的点的中心。