公开(公告)号：US10032864B2

公开(公告)日：2018-07-24

申请号：US15292515

申请日：2016-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Seok Min ,  Mi Gyeong Gwon ,  Seong Jin Nam ,  Sug Hyun Sung ,  Young Hoon Song ,  Young Mook Oh

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L21/311 ,  H01L29/165 ,  H01J37/32

Abstract: Semiconductor devices are provided. The semiconductor device includes a first fin and a second fin on a substrate and a field insulation layer between the first fin and the second fin. The field insulation layer include a first insulation layer and a second insulation layer on the first insulation layer and connected to the first insulation layer. The second insulation layer is wider than the first insulation layer. A ratio of a top width to a bottom width of each of the first fin and the second fin exceeds 0.5.

公开(公告)号：US10002967B2

公开(公告)日：2018-06-19

申请号：US15602131

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Soo Hong ,  Jeong Yun Lee ,  Kyung Seok Min ,  Seung Ju Park ,  Geum Jung Seong ,  Bo Ra Lim

IPC: H01L21/70 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7855 ,  H01L29/0611 ,  H01L29/0657 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7854

Abstract: Semiconductor devices as described herein may include a fin-shaped pattern extending in a first direction, first and second side walls facing each other, first and second gate electrodes extending in a second direction and spaced apart from each other, a first gate spacer that is on a side wall of the first gate electrode, a second gate spacer that is on a side wall of the second gate electrode, a first trench in the fin-shaped pattern that is between the first and second gate electrodes and having a first width, and a second trench in the fin-shaped pattern that is below the first trench and has a second width smaller than the first width. The fin-shaped pattern may include first and second inflection points on the side walls of the fin-shaped pattern, and a bottom surface of the second trench may be lower than the inflection points.

公开(公告)号：US20180069125A1

公开(公告)日：2018-03-08

申请号：US15602131

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Soo Hong ,  Jeong Yun Lee ,  Kyung Seok Min ,  Seung Ju Park ,  Geum Jung Seong ,  Bo Ra Lim

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7855 ,  H01L29/0611 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7854

Abstract: Semiconductor devices as described herein may include a fin-shaped pattern extending in a first direction, first and second side walls facing each other, first and second gate electrodes extending in a second direction and spaced apart from each other, a first gate spacer that is on a side wall of the first gate electrode, a second gate spacer that is on a side wall of the second gate electrode, a first trench in the fin-shaped pattern that is between the first and second gate electrodes and having a first width, and a second trench in the fin-shaped pattern that is below the first trench and has a second width smaller than the first width. The fin-shaped pattern may include first and second inflection points on the side walls of the fin-shaped pattern, and a bottom surface of the second trench may be lower than the inflection points.

公开(公告)号：US09876013B1

公开(公告)日：2018-01-23

申请号：US15477554

申请日：2017-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Ju Park ,  Jeong Yun Lee ,  Kyung Seok Min ,  Geum Jung Seong ,  Bo Ra Lim ,  Seung Soo Hong

IPC: H01L23/48 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/42356 ,  H01L29/66545

Abstract: A semiconductor device is provided including first and second active fin arrays on a substrate. The semiconductor device further includes a pair of first gate spacers disposed on the first and second active fin arrays, each of the pair of first gate spacers including a first region having a first width, a second region having a second width, and a third region between the first region and the second region and having a third width; and first and second gate electrodes, the first gate electrode disposed between the first regions and the second gate electrode disposed between the second regions. The first regions are on the first active fin array, the second regions are on the second active fin array, and the third regions are between the first active fin array and the second active fin array. Each of the first and second widths is greater than the third width.