公开(公告)号：US20230335467A1

公开(公告)日：2023-10-19

申请号：US18341087

申请日：2023-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUBIN SEO ,  KWANGJIN MOON ,  KUNSANG PARK ,  MYUNGJOO PARK ,  SUJEONG PARK ,  JAEWON HWANG

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/49816 ,  H01L2225/06548 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.

公开(公告)号：US20210320077A1

公开(公告)日：2021-10-14

申请号：US17108140

申请日：2020-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUBIN SEO ,  SUJEONG PARK ,  KWANGJIN MOON ,  MYUNGJOO PARK

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, an under-bump pattern on the semiconductor substrate and including a first metal, a bump pattern on the under-bump pattern, and an organic dielectric layer on the semiconductor substrate and in contact with a sidewall of the bump pattern. The bump pattern includes a support pattern in contact with the under-bump pattern and having a first width, and a solder pillar pattern on the support pattern and having a second width. The first width is greater than the second width. The support pattern includes at least one of a solder material and an intermetallic compound (IMC). The intermetallic compound includes the first metal and the solder material.

公开(公告)号：US20220037236A1

公开(公告)日：2022-02-03

申请号：US17316970

申请日：2021-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUBIN SEO ,  KWANGJIN MOON ,  KUNSANG PARK ,  MYUNGJOO PARK ,  SUJEONG PARK ,  JAEWON HWANG

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.

公开(公告)号：US20210351112A1

公开(公告)日：2021-11-11

申请号：US17381287

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNGJOO PARK ,  JAEWON HWANG ,  KWANGJIN MOON ,  KUNSANG PARK

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.