公开(公告)号：US10475501B2

公开(公告)日：2019-11-12

申请号：US15946992

申请日：2018-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Yeon Jeon ,  Ah Chan Kim ,  Min Joung Lee ,  Youn-Sik Choi

IPC: G11C7/10 ,  G11C11/34 ,  H03M9/00 ,  G06F13/28 ,  G06F11/34

Abstract: A semiconductor device includes a first serializer configured to collect at least one event in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period, a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items, a timer configured to provide a clock signal having a second period, a direct memory access (DMA) configured to capture the first parallel data items periodically at a second period using the clock signal to generate capture data items, and a first memory configured to store the capture data items. The addresses of the first memory at which the respective capture data items are stored are arranged in an order that the respective capture data items are captured.

公开(公告)号：US10209734B2

公开(公告)日：2019-02-19

申请号：US15415162

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Joung Lee ,  Suk Nam Kwon ,  Jae Gon Lee

IPC: G06F1/32 ,  G06F1/04 ,  G06F21/72

Abstract: A clock management unit (CMU) includes a first clock control circuit controlling a first clock source, a second clock control circuit sending a first clock request to the first clock control circuit in response to an intellectual property (IP) block clock request from an IP block and controlling a second clock source, and a CMU controller. The second clock source receives a clock signal from the first clock source. A power management unit (PMU) sends a PMU clock request to the CMU controller. The CMU provides the clock signal to the IP block in response to the PMU clock request.

公开(公告)号：US10429881B2

公开(公告)日：2019-10-01

申请号：US15415020

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Joung Lee ,  Se Hun Kim ,  Jae Gon Lee

IPC: G06F1/04 ,  G06F1/3203 ,  G06F21/00 ,  G06F21/71

Abstract: A semiconductor device includes a first clock control circuit for controlling a first clock source; a second clock control circuit for sending a first clock request to the first clock control circuit in response to a block clock request from an intellectual property (IP) block, and controlling a second clock source, which receives a clock signal from the first clock source, to generate a stopped clock signal, which is a clock signal turned off for a predetermined amount of time; and a driver circuit for receiving a block control signal, and outputting the block control signal to the IP block while the short stopped clock signal is output to the IP block.

公开(公告)号：US10296066B2

公开(公告)日：2019-05-21

申请号：US15415106

申请日：2017-01-25

Applicant: Samsung Electronics Co., LTD.

Inventor： Ah Chan Kim ,  Jae Gon Lee ,  Min Joung Lee

IPC: H04J3/06 ,  G06F1/3234 ,  G06F13/42 ,  G06F1/06 ,  H04J3/14 ,  H04L12/933

Abstract: A system on chip (SoC) includes a control circuit configured to determine whether a requested operating mode is one of a functional mode and a monitoring mode. The control circuit is configured to provide a request signal to at least one clock circuit to request at least one clock signal and selectively output one of the at least one clock signal in response to at least one acknowledgment signal received from the at least one clock circuit, when the requested operating mode is the functional mode. The control circuit is configured to selectively output one of the at least one clock signal without providing the request signal, when the requested operating mode is the monitoring mode.