公开(公告)号：US09830960B2

公开(公告)日：2017-11-28

申请号：US15294890

申请日：2016-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-kyo Lee ,  Won-young Lee ,  Bo-bae Shin ,  Jung-hwan Choi ,  Yong-cheol Bae ,  Seok-hun Hyun ,  Min-su Ahn

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

Abstract: A memory device may include a data output circuit configured to multiplex a plurality of data signals read from a memory cell array, wherein the data output circuit includes a clock boosting circuit configured to receive a plurality of internal clock signals generated based on a first power voltage, and to generate a plurality of boosted clock signals by boosting the plurality of internal clock signals based on a second power voltage having a voltage level greater than that of the first power voltage, and a data output driver configured to multiplex and output the plurality of data signals synchronized with the boosted clock signals.