公开(公告)号：US12063044B2

公开(公告)日：2024-08-13

申请号：US18189599

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsun Lee ,  Jaewoo Park ,  Myoungbo Park ,  Jinook Jung ,  Junghwan Choi

IPC: H03L7/093 ,  H03L7/081 ,  H03L7/099

CPC classification number: H03L7/093 ,  H03L7/0818 ,  H03L7/0991

Abstract: A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.