公开(公告)号：US20130176782A1

公开(公告)日：2013-07-11

申请号：US13783877

申请日：2013-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo Sub LEE ,  Pan Suk KWAK

IPC: G11C16/04

CPC classification number: G11C5/063 ,  G11C7/18 ,  G11C16/04 ,  H01L27/11573

Abstract: A memory device includes; a memory cell array including a memory cell connected to a bit line, a page buffer unit receiving data from the memory cell via the bit line, and a contact unit providing an electrical path through which the data is communicated from the memory cell array to the page buffer unit, wherein the contact unit comprises a sub-bit line configured to connect the bit line via a first contact with the page buffer unit via a second contact.

Abstract translation: 存储装置包括： 包括连接到位线的存储单元的存储单元阵列，经由位线从存储单元接收数据的页缓冲器单元，以及提供数据从存储单元阵列传送到电路的电路的接触单元 页面缓冲单元，其中所述接触单元包括被配置为经由第二接触件经由第一接触与所述页面缓冲单元连接所述位线的子位线。

公开(公告)号：US20220190131A1

公开(公告)日：2022-06-16

申请号：US17409681

申请日：2021-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Min KO ,  Myung Hun LEE ,  Pan Suk KWAK ,  Dae Seok BYEON

IPC: H01L29/423 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522

Abstract: A nonvolatile memory device includes a peripheral logic structure including a peripheral circuit on a substrate, a horizontal semiconductor layer extending along an upper surface of the peripheral logic structure, stacked structures arranged in a first direction on the horizontal semiconductor layer and including interlayer insulating films and conductive films alternately stacked in a direction perpendicular to the substrate, a first opening disposed between the stacked structures and included in the horizontal semiconductor layer to expose a part of the peripheral logic structure and a second opening arranged in a second direction, which differs from the first direction, from the first opening, included in the horizontal semiconductor layer, and disposed adjacent to the first opening. The peripheral logic structure includes a control transistor overlapping the second opening in a plan view and controlling operation of the plurality of stacked structures.