公开(公告)号：US20220157736A1

公开(公告)日：2022-05-19

申请号：US17590238

申请日：2022-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Rakhwan KIM ,  Eun-Ji JUNG

IPC: H01L23/532 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

公开(公告)号：US20240145388A1

公开(公告)日：2024-05-02

申请号：US18409447

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Kyu HAN ,  Myeongsoo LEE ,  Rakhwan KIM ,  Woojin JANG

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/092

Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.

公开(公告)号：US20210183786A1

公开(公告)日：2021-06-17

申请号：US16940933

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Rakhwan KIM ,  Eun-Ji JUNG

IPC: H01L23/532 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/768

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

公开(公告)号：US20240178061A1

公开(公告)日：2024-05-30

申请号：US18339569

申请日：2023-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghee SEO ,  Rakhwan KIM ,  Jeongik KIM ,  Chunghwan SHIN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76876 ,  H01L21/7684 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53266

Abstract: An integrated circuit device includes a middle insulating structure on a substrate, a first contact structure passing through the middle insulating structure and extending by a first vertical length from a top surface of the middle insulating structure toward the substrate, and a second contact structure passing through the middle insulating structure. The middle insulating structure may have a top surface extending in a lateral direction at a first vertical level. The second contact structure may extend by a second vertical length greater than the first vertical length from the top surface of the middle insulating structure toward the substrate. The first contact structure may have a first top surface extending planar along an extension line of the top surface of the middle insulating structure. The second contact structure may have a second top surface, which may be convex in a direction away from the substrate.

公开(公告)号：US20240339395A1

公开(公告)日：2024-10-10

申请号：US18494183

申请日：2023-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungchul KANG ,  Rakhwan KIM ,  Jeongik KIM ,  Chunghwan SHIN ,  Daeun KIM ,  Seongdong LIM

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/092

Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a gate contact structure electrically connected to the outer electrode. The gate contact structure may include a lower gate contact on a top surface of the outer electrode and an upper gate contact on the lower gate contact. The lower gate contact may include a first liner pattern, a first filling pattern on the first liner pattern, and a nucleation pattern between the first liner pattern and the first filling pattern. The upper gate contact may not include the nucleation pattern.

公开(公告)号：US20230170296A1

公开(公告)日：2023-06-01

申请号：US17961056

申请日：2022-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anthony Dongick LEE ,  Sangcheol NA ,  Kichul PARK ,  Doohwan PARK ,  Kyoungwoo LEE ,  Rakhwan KIM ,  Yoonsuk KIM ,  Jinnam KIM ,  Hoonjoo NA ,  Eunji JUNG ,  Juyoung JUNG

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/53238 ,  H01L23/53223 ,  H01L23/53266

Abstract: A semiconductor device includes a substrate. A wiring layer is over the substrate. A first via structure directly contacts a lower portion of the wiring layer. A second via structure directly contacts an upper portion of the wiring layer. The first via structure generates first stress in the wiring layer. The second via structure generates second stress in the wiring layer. The second stress is of an opposite type to the first stress. The first stress and the second stress compensate for each other in the wiring layer.