公开(公告)号：US20240427405A1

公开(公告)日：2024-12-26

申请号：US18749071

申请日：2024-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo LEE ,  Sooyong KIM ,  Younghoon LEE ,  Jongjin LEE ,  Junho HUH

IPC: G06F1/324

Abstract: A Dynamic Voltage and Frequency Scaling (DVFS) controller, an integrated circuit including DVFS, and a method of operating the DVFS controller are provided. The integrated circuit includes at least one subblock circuit configured to process an instruction, and a DVFS controller configured to control a power management unit (PMU) and a clock management unit (CMU) to control an operating voltage and an operating frequency, respectively, based on a resonance frequency calculated from a frequency response resulting from dynamic characteristics of an entire power system including the PMU, a power delivery network (PDN), and the subblock circuit.

公开(公告)号：US20240274676A1

公开(公告)日：2024-08-15

申请号：US18221693

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin LEE ,  Sooyoung PARK ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device including: a channel structure; a 1st source/drain region on the channel structure; and an enlarged backside contact structure connected to the 1st source/drain region, wherein the enlarged backside contact structure includes a backside contact structure below the 1st source/drain region, a 1st side via structure at a 1st side of the 1st source/drain region, and a 1st front contact structure above the 1st source/drain region, and wherein the backside contact structure is connected to the 1st side via structure, which is connected to the front contact structure.

公开(公告)号：US20230343839A1

公开(公告)日：2023-10-26

申请号：US17885237

申请日：2022-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Sung KIM ,  Jaejik BAEK ,  Wonhyuk HONG ,  Myunghoon JUNG ,  Jongjin LEE ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/40

CPC classification number: H01L29/4175 ,  H01L23/5286 ,  H01L29/401 ,  H01L29/0673

Abstract: Provided is a semiconductor device that includes: at least one transistor, a front side structure, and a back side structure, the front side structure being disposed opposite to the back side structure with respect to the transistor; and a front via formed at a side of the transistor and connecting the front side structure to the back side structure, wherein the front via is formed in a via hole formed of a lower via hole and an upper via hole vertically connected to each other, and wherein the via hole has a bent structure at a side surface thereof where the lower via hole is connected to the upper via hole.

公开(公告)号：US20220157736A1

公开(公告)日：2022-05-19

申请号：US17590238

申请日：2022-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Rakhwan KIM ,  Eun-Ji JUNG

IPC: H01L23/532 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

公开(公告)号：US20240105615A1

公开(公告)日：2024-03-28

申请号：US18110296

申请日：2023-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongjin LEE ,  Wonhyuk HONG ,  Kang-Ill SEO

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Provided is field-effect transistor structure including: a channel structure; a source/drain region and a 2nd source/drain region connected to each other through the channel structure; a 1st contact plug, on a top surface of the 1st source/drain region, connected to a voltage source or 1st circuit element through a back-end-of-line (BEOL) structure; and a 2nd contact plug, on a bottom surface of the 2nd source/drain region, connected to the 1st voltage source, through a backside power rail, or another circuit element, wherein the 1st source/drain region and the 2nd source/drain region have a substantially same height.

公开(公告)号：US20240290866A1

公开(公告)日：2024-08-29

申请号：US18540280

申请日：2023-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Taesun KIM ,  Myunghoon JUNG ,  Kang-ill SEO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A system and a method are disclosed for forming a bottle-neck shaped backside contact structure in a semiconductor device, wherein the bottle-neck shaped backside contact structure has a first side partially within the first source/drain structure, a second side contacting a backside power rail, and a liner extending from the first side to the backside power rail. The liner includes a first region comprised of either a Ta silicide liner or a Ti silicide liner, a second region comprised of a Ti/TiN liner and a third region comprised of either a Ta silicide liner or a Ti silicide liner. The backside contact structure includes a first portion having a positive slope and a second portion, adjacent to the first portion, having no slope.

公开(公告)号：US20240203882A1

公开(公告)日：2024-06-20

申请号：US18197381

申请日：2023-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongjin LEE ,  Jaejik BAEK ,  Myunghoon JUNG ,  Kang-ill SEO

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Provided is a method of manufacturing an integrated circuit device. The method includes forming a semiconductor device, wherein the semiconductor device has one or more source/drain structures, one or more channel structures and wherein the substrate is on a first side of the semiconductor device. The method also includes forming a back-end-of-line (BEOL) region and forming a bottle-neck shaped backside contact structure in the substrate and in contact with a first source/drain structure of the semiconductor device, wherein the bottle-neck shaped backside contact structure has a first side contacting the first source/drain structure, a second side contacting a backside power rail, and sidewalls extending from the first source/drain structure to the backside power rail; and wherein the backside contact structure has a first region having a positive slope and a second region, adjacent to the first region, having no slope.

公开(公告)号：US20230378839A1

公开(公告)日：2023-11-23

申请号：US18229520

申请日：2023-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunsuk KO ,  Unyong LEE ,  Jinwoo CHO ,  Jungin MIN ,  Jongjin LEE

IPC: H02K3/52 ,  D06F23/02 ,  D06F37/22 ,  D06F37/30 ,  D06F37/20

CPC classification number: H02K3/522 ,  D06F23/02 ,  D06F37/22 ,  D06F37/304 ,  D06F37/206 ,  H02K2203/12

Abstract: A washing machine including a tub, a stator fastenable to a rear of the tub, and a rotor to electromagnetically interact with the stator and rotate around a rotating shaft, where the stator includes a stator core, an insulator configured to surround the stator core, and a bracket fastenable to the insulator, and fastenable to the rear of the tub such that while the stator is to the tub the stator is fastened to the rear of the tub through the bracket while the bracket is fastened to the insulator and the rear of the tub.

公开(公告)号：US20220286054A1

公开(公告)日：2022-09-08

申请号：US17575249

申请日：2022-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwook PARK ,  Joonseok PARK ,  Jongjin LEE ,  Horang JANG

IPC: H02M3/158 ,  H02M3/157 ,  G06F13/42

Abstract: An electronic device includes a system on chip (SoC) and a power management integrated circuit (PMIC). The SoC includes a plurality of power domains and a dynamic voltage and frequency scaling (DVFS) controller which performs DVFS on the power domains The PMIC includes direct current (DC)-DC converters and a control logic which controls the plurality of DC-DC converters, and each of the DC-DC converters provides a corresponding output voltage to a respective one of the power domains. The control logic designates a target DC-DC converter which provides a target output voltage having a target level as a global DC-DC converter and provides the target output voltage to a power domain corresponding the global DC-DC converter and to at least one first power domain consuming the target output voltage, from among the plurality of power domains, by sharing the target output voltage provided by the global DC-DC converter.

公开(公告)号：US20210183786A1

公开(公告)日：2021-06-17

申请号：US16940933

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Rakhwan KIM ,  Eun-Ji JUNG

IPC: H01L23/532 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/768

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.