公开(公告)号：US20220157736A1

公开(公告)日：2022-05-19

申请号：US17590238

申请日：2022-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Rakhwan KIM ,  Eun-Ji JUNG

IPC: H01L23/532 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

公开(公告)号：US20230282512A1

公开(公告)日：2023-09-07

申请号：US17991090

申请日：2022-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Wook KIM ,  Seung Yong YOO ,  Eui Bok LEE ,  Jin Nam KIM ,  Eun-Ji JUNG

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76844 ,  H01L23/535 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895

Abstract: A semiconductor device is provided. The semiconductor device includes: a lower line structure; an upper interlayer insulating film provided on the lower line structure and having a trench formed therein, wherein the trench includes a wiring line trench and a via trench extending from the wiring line trench to the lower line structure; and an upper line structure provided in the line trench, wherein the upper line structure includes an upper barrier film and an upper filling film. The upper filling film includes a first sub-filling film in contact with the upper interlayer insulating film, and a second sub-filling film provided on the first sub-filling film. The first sub-filling film fills an entirety of the upper via trench and covers at least a portion of a bottom surface of the upper wiring line trench.

公开(公告)号：US20240153848A1

公开(公告)日：2024-05-09

申请号：US18351779

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Yong YOO ,  Eun-Ji JUNG

IPC: H01L23/48

CPC classification number: H01L23/481

Abstract: A semiconductor device may include an upper interlayer insulating film on a lower wiring structure and an upper wiring structure in an upper wiring trench of the upper interlayer insulating film. The lower wiring structure may include a lower filling film and a lower capping film including a capping opening exposing a portion of the lower filling film. The upper wiring structure may contact the lower filling film. The upper wiring structure may include an upper liner between an upper barrier film and an upper filling film. A sidewall portion of the upper liner may include cobalt doped with ruthenium. A bottom portion of the upper liner may not include cobalt doped with ruthenium. A sidewall portion of the upper barrier film may include tantalum nitride doped with ruthenium (Ru). A sidewall portion of the upper barrier film may not be in contact with the lower capping film.

公开(公告)号：US20210183786A1

公开(公告)日：2021-06-17

申请号：US16940933

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Rakhwan KIM ,  Eun-Ji JUNG

IPC: H01L23/532 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/768

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.