公开(公告)号：US20230307371A1

公开(公告)日：2023-09-28

申请号：US17981119

申请日：2022-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Youn SEO ,  Sang Ho RHA ,  Tae-Jong HAN

IPC: H01L23/535 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L23/535 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit substrate, a peripheral circuit element on the peripheral circuit substrate, and a wiring structure connected to the peripheral circuit element and a memory cell structure provided on the peripheral circuit structure. The memory cell structure includes a cell substrate including a cell array region, an extended region, and a through region, a mold structure including a plurality of gate electrodes sequentially provided on the cell array region and on the extended region in a step form, and a plurality of mold sacrifice films sequentially provided on the through region, a channel structure intersecting the plurality of gate electrodes on the cell array region, and a cell contact penetrating the mold structure on the extended region and configured to connect at least one of the plurality of gate electrodes and the wiring structure.

公开(公告)号：US20230146542A1

公开(公告)日：2023-05-11

申请号：US17828580

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Jae OH ,  Ik Soo KIM ,  Sang Ho RHA ,  Ji Woon IM

IPC: H01L27/108

CPC classification number: H01L27/10811 ,  H01L27/10885 ,  H01L27/10894

Abstract: A semiconductor memory device includes a cell substrate, a mold structure including a plurality of gate electrodes stacked on the cell substrate, the gate electrodes including a first ground selection line, a second ground selection line and a plurality of word lines, which are sequentially stacked, a channel structure that extends in a vertical direction that crosses an upper surface of the cell substrate and penetrates the mold structure, a partial isolation region that extends in a first direction that is parallel with the upper surface of the cell substrate and partially separates the mold structure, and a ground isolation structure that connects two partial isolation regions adjacent to each other in the first direction, extends in the vertical direction and penetrates the first ground selection line and the second ground selection line, wherein a width of the ground isolation structure increases with distance from the cell substrate.

公开(公告)号：US20200211847A1

公开(公告)日：2020-07-02

申请号：US16578245

申请日：2019-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Youn SEO ,  Ji Woon IM ,  Dai Hong KIM ,  Ik Soo KIM ,  Sang Ho RHA

IPC: H01L21/033 ,  H01L21/02

Abstract: A method of fabricating a semiconductor device and a semiconductor processing apparatus are provided. The method of fabricating a semiconductor device comprises preparing a semiconductor substrate having a front side and a back side, opposing each other, and forming a material layer on the semiconductor substrate. The material layer is formed on at least a portion of the back side of the semiconductor substrate while being formed on the front side of the semiconductor substrate. The material layer formed on the at least a portion of the back side of the semiconductor substrate is removed, while the material layer formed on the front side of the semiconductor substrate remains. A semiconductor process is performed to fabricate the semiconductor device using the material layer remaining on the front side of the semiconductor substrate.