公开(公告)号：US10990327B2

公开(公告)日：2021-04-27

申请号：US16687265

申请日：2019-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Ryong Park

IPC: G11C7/00 ,  G06F3/06 ,  G11C16/26 ,  H03M13/11 ,  G11C16/04

Abstract: A memory controller includes an error correction code (ECC) module for performing ECC decoding based on read data received from a non-volatile memory device for performing an on-chip valley search (OVS) read operation. A read voltage modification module receives status bits representing a latch that latches the read data among a plurality of latches included in the non-volatile memory device to store result values of the OVS read operation and determine whether to change a read voltage based on the status bits when the ECC decoding is successfully performed.

公开(公告)号：US11011233B2

公开(公告)日：2021-05-18

申请号：US16442670

申请日：2019-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jin Kim ,  Sang-Ryong Park ,  Jong-Nam Baek ,  Sejeong Jang

IPC: G11C16/04 ,  G11C16/08 ,  G06F3/06 ,  G06F12/02 ,  G11C16/16 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array that includes memory blocks, wherein each of the memory blocks includes pages each including memory cells, a row decoder circuit that selects one of the pages from a selected memory block of the memory blocks in a write operation and selects memory cells of a close unit from the selected memory block in a close operation, and a page buffer circuit that writes data into memory cells of a page selected by the row decoder circuit in the write operation and writes dummy data into the memory cells of the close unit selected by the row decoder circuit in the close operation. The close unit includes one or more pages, and, in the close operation, the row decoder circuit adjusts a size of the close unit.

公开(公告)号：US11550503B2

公开(公告)日：2023-01-10

申请号：US16899968

申请日：2020-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Ryong Park ,  Soo-Woong Lee ,  Youn-Soo Cheon

IPC: G06F3/06 ,  G01K13/00 ,  G06F9/4401 ,  G01K3/00

Abstract: A storage device includes a memory and a memory controller which transmits a command to the memory. The memory includes at least one memory cell array, a memory temperature sensor which measures a temperature of the memory, and a control logic. The control logic outputs a busy signal in response to the command, receives the temperature of the memory from the memory temperature sensor in response to the command, and determines whether to perform a command operation according to the command on the memory cell array based on the received temperature of the memory.

公开(公告)号：US20210096775A1

公开(公告)日：2021-04-01

申请号：US16899968

申请日：2020-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Ryong Park ,  Soo-Woong Lee ,  Youn-Soo Cheon

IPC: G06F3/06 ,  G06F9/4401 ,  G01K3/00 ,  G01K13/00

Abstract: A storage device includes a memory and a memory controller which transmits a command to the memory. The memory includes at least one memory cell array, a memory temperature sensor which measures a temperature of the memory, and a control logic. The control logic outputs a busy signal in response to the command, receives the temperature of the memory from the memory temperature sensor in response to the command, and determines whether to perform a command operation according to the command on the memory cell array based on the received temperature of the memory.