公开(公告)号：US20250069682A1

公开(公告)日：2025-02-27

申请号：US18665817

申请日：2024-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonyoung Jang ,  Taewon Kim ,  Sanghee Kang ,  Taeyun Kim

IPC: G11C29/00 ,  G11C29/56

Abstract: A memory device including a repair circuit and an operating method of the memory device are provided. The operating method includes outputting a signal representing a pre-decoded faulty row address based on predecoding a faulty row address, outputting a signal representing a pre-decoded row address based on predecoding a row address, outputting hit signals based on comparing a bit value of the pre-decoded faulty row address with a bit value of the pre-decoded row address, outputting a repair enable signal based on the hit signals, and performing a row repair operation based on the repair enable signal.

公开(公告)号：US20240348162A1

公开(公告)日：2024-10-17

申请号：US18677097

申请日：2024-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon LEE ,  Sanghee Kang ,  Hobin Yi ,  Hocheol Chung ,  Woojin Han

IPC: H02M3/07 ,  H02M1/00 ,  H02M3/158

CPC classification number: H02M3/07 ,  H02M1/007 ,  H02M3/158

Abstract: A voltage converter includes: a plurality of switches, a switch controller, a first flying capacitor and a second flying capacitor connected to the first flying capacitor, and a third flying capacitor and a fourth flying capacitor each being connected to an output node. The switch controller controls the plurality of switches to alternately perform a first operation and a second operation in order to allow the voltage source to generate a first input voltage.

公开(公告)号：US20240290414A1

公开(公告)日：2024-08-29

申请号：US18515681

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taewon Kim ,  Sanghee Kang ,  Kiho Hyun ,  Taeyun Kim

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/24

CPC classification number: G11C29/44 ,  G11C29/12015 ,  G11C29/24

Abstract: A method of testing a repair circuit of a memory device. The method may include storing first addresses in a first register of the repair circuit, wherein the first register is configured to store faulty addresses during a normal operation of the memory device, and the repair circuit is configured to perform a repair operation to replace the faulty addresses with redundancy addresses, storing test addresses in a second register of the repair circuit, wherein the test addresses are provided from a test host, outputting hit signals by comparing bit values of the addresses stored in the first register with bit values of the addresses stored in the second register, outputting repair enable signals based on the hit signals, and determining a status of a path where the repair enable signals are generated based on logic levels of the repair enable signals.