公开(公告)号：US20240071899A1

公开(公告)日：2024-02-29

申请号：US18450836

申请日：2023-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuho KANG ,  Hyungjun PARK ,  Seonghoon BAE ,  Sanghyuck OH ,  Kwangok JEONG ,  Juil CHOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49866 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5383 ,  H01L25/105 ,  H01L24/16

Abstract: Provided is a semiconductor package. The semiconductor package including a redistribution structure including a plurality of redistribution conductive patterns, a plurality of conductive vias connected to at least one of the plurality of redistribution conductive patterns, a plurality of lower pads connected to the plurality of conductive vias, and a plurality of redistribution insulation layers and the plurality of redistribution conductive patterns alternating each other, a semiconductor chip arranged on the redistribution structure, and an external connection terminal attached to the plurality of lower surface pads of the redistribution structure, wherein each of the plurality of redistribution conductive patterns includes a metal layer including copper and a skin layer arranged on an upper surface of the metal layer and including copper and nickel, may be provided.

公开(公告)号：US20240079394A1

公开(公告)日：2024-03-07

申请号：US18366054

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juil CHOI ,  Jongho PARK ,  Sanghyuck OH ,  Jaeyoung LEE ,  Jaemok JUNG ,  Hongseo HEO

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H10B80/00 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package may include a first redistribution structure, a first semiconductor chip on the first redistribution structure, a first molding layer covering the first semiconductor chip, first connection structures on the first redistribution structure and extending in a vertical direction while passing through the first molding layer, a second redistribution structure on the first semiconductor chip, a second semiconductor chip on the second redistribution structure, and a metal layer on the second semiconductor chip. The metal layer may be in contact with an upper surface of the second semiconductor chip.