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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190164922A1

    公开(公告)日：2019-05-30

    申请号：US16244661

    申请日：2019-01-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ae-nee JANG ,  KyungSeon HWANG ,  SunWon KANG

    IPC: H01L23/00 ,  H01L23/48 ,  H01L21/56

    Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

    SEMICONDUCTOR PACKAGES
    5.
    发明申请
    SEMICONDUCTOR PACKAGES 审中-公开

    公开(公告)号：US20180366456A1

    公开(公告)日：2018-12-20

    申请号：US15867686

    申请日：2018-01-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangnam JEONG ,  IlJoon Kim ,  SunWon KANG

    IPC: H01L25/16 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48

    Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210183801A1

    公开(公告)日：2021-06-17

    申请号：US17189405

    申请日：2021-03-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ae-nee JANG ,  KyungSeon HWANG ,  SunWon KANG

    IPC: H01L23/00 ,  H01L21/56 ,  H01L23/48

    Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

    HIGH-SPEED SEMICONDUCTOR MODULES
    7.
    发明申请
    HIGH-SPEED SEMICONDUCTOR MODULES 审中-公开

    公开(公告)号：US20200083195A1

    公开(公告)日：2020-03-12

    申请号：US16684569

    申请日：2019-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyoungsoo KIM ,  SunWon KANG

    IPC: H01L25/065 ,  H01L25/10 ,  H01L23/50 ,  H01L23/498

    Abstract: A semiconductor module, comprising: a module substrate with an electric connection element; at least one semiconductor package provided on the module substrate, the at least one semiconductor package including a plurality of semiconductor chips; and a connection region electrically connecting the semiconductor package to the module substrate, wherein the connection region comprises: a first region electrically connected between data signal terminals of a first chip of the semiconductor chips of the semiconductor package and the module substrate; a second region electrically connected between data signal terminals of a second chip of the semiconductor chips of the semiconductor package and the module substrate; and a third region electrically connected between command/address signal terminals of both the first and second chips of the semiconductor package and the module substrate, wherein the first region is closer to the electric connection element of the module substrate, compared with the third region.

    SEMICONDUCTOR PACKAGES
    8.
    发明申请
    SEMICONDUCTOR PACKAGES 审中-公开

    公开(公告)号：US20190295999A1

    公开(公告)日：2019-09-26

    申请号：US16438430

    申请日：2019-06-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangnam JEONG ,  IlJoon KIM ,  SunWon KANG

    IPC: H01L25/16 ,  H01L23/538 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522

    Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.

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