公开(公告)号：US20220037494A1

公开(公告)日：2022-02-03

申请号：US17189615

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junbeom PARK ,  Sangsu KIM ,  Junggil YANG

IPC: H01L29/423 ,  H01L29/417

Abstract: A semiconductor device includes a first source/drain structure having a first length in a horizontal direction, as viewed in a planar cross-sectional view, the horizontal direction being perpendicular to a vertical direction, a second source/drain structure having a second length in the horizontal direction, as viewed in the planar cross-sectional view, the second length being less than the first length, channels extending between the first source/drain structure and the second source/drain structure, the channels being spaced apart from each other in the vertical direction, at least one sacrificial pattern between adjacent ones of the channels, and a trench penetrating the channels and the at least one sacrificial pattern.

公开(公告)号：US20180174920A1

公开(公告)日：2018-06-21

申请号：US15651018

申请日：2017-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangsu KIM ,  Yunsang SHIN

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/02 ,  H01L27/06 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/02019 ,  H01L21/02065 ,  H01L21/3212 ,  H01L21/76837 ,  H01L21/8238 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device including a semiconductor substrate including first regions and second regions, at least one of the first regions being disposed between adjacent second regions; a plurality of first gate structures on the first regions of the semiconductor substrate; and a plurality of second gate structures on the second regions of the semiconductor substrate, wherein each of the first and second gate structures includes a lower gate structure including a recess region defined by sidewalls and a bottom connecting the sidewalls; and an upper gate structure including a gap-fill metal pattern that fills the recess region of the lower gate structure, wherein the bottom of the lower gate structure included in the first gate structure has a thickness different from a thickness of the bottom of the lower gate structure included in the second gate structure, and wherein the gap-fill metal patterns of the first and second gate structures have top surfaces at substantially a same level.

公开(公告)号：US20220140081A1

公开(公告)日：2022-05-05

申请号：US17577595

申请日：2022-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangsu KIM ,  Junbeom PARK ,  Junggil YANG

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device including an active pattern on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other.

公开(公告)号：US20150311286A1

公开(公告)日：2015-10-29

申请号：US14606017

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwan LEE ,  Sangsu KIM

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/3247 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7842 ,  H01L29/785

Abstract: A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

Abstract translation: 半导体器件可以包括设置在基板上以容纳硅锗的应变松弛缓冲层，设置在应变松弛缓冲层上的半导体图案，以包括源区域，漏极区域和将源极区域与漏极连接的沟道区域 区域，以及包围沟道区并在衬底和沟道区之间延伸的栅电极。 源极和漏极区域可以含有浓度为30at％或更高的锗。