公开(公告)号：US10475504B2

公开(公告)日：2019-11-12

申请号：US15334380

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Young Kim ,  Junbae Kim

IPC: H02H9/00 ,  G11C11/4078 ,  H01L27/02 ,  H01L27/108 ,  H02H9/04 ,  G11C5/14 ,  G11C11/4074

Abstract: Disclosed is an integrated protecting circuit, which detects ESD and EOS pulses to prevent an over-voltage from being applied to a semiconductor device. The integrated protecting circuit includes a first detector configured to detect an occurrence of an electrical over-stress between a first node to which a first voltage is applied and a second node to which a second voltage is applied, a second detector configured to detect an occurrence of an electrostatic discharge between the first and second nodes, a determination circuit configured to receive separate outputs of the first and second detectors at the same time and to generate a control signal, and a clamping device configured to perform a turn on/off operation in response to the control signal such that a voltage between the first and second nodes is clamped into a constant voltage.

公开(公告)号：US09240415B2

公开(公告)日：2016-01-19

申请号：US14312777

申请日：2014-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Kyung Park ,  Ki-Jae Hur ,  Hyeong-Sun Hong ,  Se-Young Kim ,  Jun-Hee Lim

IPC: H01L21/70 ,  H01L27/108 ,  H01L29/06 ,  H01L21/265 ,  H01L21/28

CPC classification number: H01L27/10897 ,  H01L21/265 ,  H01L21/28158 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/0649

Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.

Abstract translation: 提供半导体器件。 单元区域设置在基板中。 单元区域包括存储单元。 外围区域设置在基板中。 外围区域与细胞区域相邻。 外围区域具有沟槽隔离，第一有源区和第二有源区。 沟槽隔离被插入在第一有源区和第二有源区之间。 公共栅极图案设置在周边区域上。 公共栅极图案沿第一方向延伸并且部分地与第一有源区域，第二有源区域和沟槽隔离部分重叠。 掩埋导电图案被沟槽隔离封闭。 掩埋导电图案沿与第一方向交叉的第二方向延伸。 掩埋导电图案的顶表面比公共栅极图案的底表面低。

公开(公告)号：US20150008530A1

公开(公告)日：2015-01-08

申请号：US14312777

申请日：2014-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Kyung Park ,  Ki-Jae Hur ,  Hyeong-Sun Hong ,  Se-Young Kim ,  Jun-Hee Lim

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/06 ,  H01L21/265 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/10897 ,  H01L21/265 ,  H01L21/28158 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/0649

Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.

Abstract translation: 提供一种半导体器件。 单元区域设置在基板中。 单元区域包括存储单元。 外围区域设置在基板中。 外围区域与细胞区域相邻。 外围区域具有沟槽隔离，第一有源区和第二有源区。 沟槽隔离被插入在第一有源区和第二有源区之间。 公共栅极图案设置在周边区域上。 公共栅极图案沿第一方向延伸并且部分地与第一有源区域，第二有源区域和沟槽隔离部分重叠。 掩埋导电图案被沟槽隔离封闭。 掩埋导电图案沿与第一方向交叉的第二方向延伸。 掩埋导电图案的顶表面比公共栅极图案的底表面低。