公开(公告)号：US09484203B2

公开(公告)日：2016-11-01

申请号：US14535437

申请日：2014-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Hee Lim ,  Ki-Jae Hur ,  Sung-Hwan Kim ,  Hae-In Jung ,  Soo-Jin Hong

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L29/4236 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78

Abstract: In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An ion implantation process is performed at an upper portion of the substrate exposed by the gate structure, so that an ion implantation region is formed to have an expanded volume. The ion implantation process uses ions that are identical to a material of the substrate.

Abstract translation: 在制造半导体器件的方法中，在衬底上形成栅极结构。 在由栅极结构暴露的衬底的上部进行离子注入工艺，使得形成离子注入区域以具有膨胀的体积。 离子注入工艺使用与衬底材料相同的离子。

公开(公告)号：US09240415B2

公开(公告)日：2016-01-19

申请号：US14312777

申请日：2014-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Kyung Park ,  Ki-Jae Hur ,  Hyeong-Sun Hong ,  Se-Young Kim ,  Jun-Hee Lim

IPC: H01L21/70 ,  H01L27/108 ,  H01L29/06 ,  H01L21/265 ,  H01L21/28

CPC classification number: H01L27/10897 ,  H01L21/265 ,  H01L21/28158 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/0649

Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.

Abstract translation: 提供半导体器件。 单元区域设置在基板中。 单元区域包括存储单元。 外围区域设置在基板中。 外围区域与细胞区域相邻。 外围区域具有沟槽隔离，第一有源区和第二有源区。 沟槽隔离被插入在第一有源区和第二有源区之间。 公共栅极图案设置在周边区域上。 公共栅极图案沿第一方向延伸并且部分地与第一有源区域，第二有源区域和沟槽隔离部分重叠。 掩埋导电图案被沟槽隔离封闭。 掩埋导电图案沿与第一方向交叉的第二方向延伸。 掩埋导电图案的顶表面比公共栅极图案的底表面低。

公开(公告)号：US20150008530A1

公开(公告)日：2015-01-08

申请号：US14312777

申请日：2014-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Kyung Park ,  Ki-Jae Hur ,  Hyeong-Sun Hong ,  Se-Young Kim ,  Jun-Hee Lim

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/06 ,  H01L21/265 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/10897 ,  H01L21/265 ,  H01L21/28158 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/0649

Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.

Abstract translation: 提供一种半导体器件。 单元区域设置在基板中。 单元区域包括存储单元。 外围区域设置在基板中。 外围区域与细胞区域相邻。 外围区域具有沟槽隔离，第一有源区和第二有源区。 沟槽隔离被插入在第一有源区和第二有源区之间。 公共栅极图案设置在周边区域上。 公共栅极图案沿第一方向延伸并且部分地与第一有源区域，第二有源区域和沟槽隔离部分重叠。 掩埋导电图案被沟槽隔离封闭。 掩埋导电图案沿与第一方向交叉的第二方向延伸。 掩埋导电图案的顶表面比公共栅极图案的底表面低。

公开(公告)号：US09269810B2

公开(公告)日：2016-02-23

申请号：US14444155

申请日：2014-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Uk Han ,  Won-Kyung Park ,  Jun-Ho Park ,  Jun-Hee Lim ,  Ki-Jae Hur

IPC: G11C5/02 ,  H01L29/78 ,  H01L27/088 ,  G11C7/06 ,  G11C16/26 ,  G11C11/4091

CPC classification number: H01L29/7835 ,  G11C5/025 ,  G11C7/065 ,  G11C11/4091 ,  G11C16/26 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: A semiconductor device includes an active region defined on a substrate, a gate electrode disposed on the active region and covering two adjacent corners of the active region, a drain area formed in the active region adjacent to a first side of the gate electrode, and a source area formed in the active region adjacent to a second side of the gate electrode. The first and second sides of the gate electrode are spaced apart from each other, and the first side has a bent shape.

Abstract translation: 半导体器件包括限定在衬底上的有源区，设置在有源区上并覆盖有源区的两个相邻角的栅电极，形成在与栅电极的第一侧相邻的有源区中的漏区，以及 源极区域形成在与栅电极的第二侧相邻的有源区域中。 栅电极的第一和第二侧彼此间隔开，第一侧具有弯曲形状。