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公开(公告)号：US20240324194A1
公开(公告)日：2024-09-26
申请号：US18602778
申请日：2024-03-12
发明人： Dongjin LEE , Junhee LIM , Hakseon KIM , Kangoh YUN , Sohyun LEE
CPC分类号： H10B41/35 , G11C16/0483 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/41 , H10B80/00 , H01L2225/06506
摘要： An integrated circuit device includes a substrate including an active region including a central active region, base active regions and extended active regions integrated together and defined by a device isolation film. A drain region is located in the central active region, and source regions are respectively located in the base active regions. The base active regions are spaced apart from each other in different diagonal directions with respect to the central active region in a plan view. The extended active regions each have an L-shape, connect the central active region and the base active regions, and are spaced apart from each other. Gate structures that respectively cross the base active regions and are spaced apart from each other on the substrate. The central active region, the extended active regions, the base active regions, and the gate structures configure pass transistors, and the pass transistors share the drain region.
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公开(公告)号：US20230389322A1
公开(公告)日：2023-11-30
申请号：US18133278
申请日：2023-04-11
发明人： Dongjin LEE , Junhee LIM , Donghoon KWON , Hakseon KIM , Nakjin SON , Yanghee LEE , Juhyun LEE
摘要： A semiconductor device includes a peripheral circuit region including a first substrate, circuit elements on the first substrate, a first interconnection structure electrically connected to the circuit elements, first to fourth peripheral region insulating layer; and a memory cell region including a second substrate on the peripheral circuit region and having a first region and a second region, gate electrodes stacked on the first region, a cell region insulating layer covering the gate electrodes, channel structures passing through the gate electrodes, and a second interconnection structure electrically connected to the gate electrodes and the channel structures. The peripheral circuit region further includes first to fourth lower protective layers, at least one of the first, second, third and fourth lower protective layers includes a hydrogen diffusion barrier layer configured to inhibit a hydrogen element included in the cell region insulating layer from diffusing to the circuit elements, and including aluminum oxide.
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公开(公告)号：US20210028283A1
公开(公告)日：2021-01-28
申请号：US16822389
申请日：2020-03-18
发明人： Sungkweon BAEK , Taeyoung KIM , Hakseon KIM , Kangoh YUN , Changhoon JEON , Junhee LIM
IPC分类号： H01L29/10 , H01L29/423
摘要： A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.
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公开(公告)号：US20180358056A1
公开(公告)日：2018-12-13
申请号：US15854551
申请日：2017-12-26
发明人： Kilho LEE , Gwanhyeob KOH , Junhee LIM , Hongsoo KIM , Chang-hoon JEON
IPC分类号： G11C5/06 , G11C16/04 , G11C11/16 , H01L25/18 , H01L27/1157 , H01L27/22 , H01L27/11573 , H01L43/10
CPC分类号： G11C5/06 , G11C11/005 , G11C11/161 , G11C13/0002 , G11C13/0004 , G11C16/0483 , G11C2213/72 , G11C2213/76 , H01L25/18 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/222 , H01L43/10
摘要： A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.
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公开(公告)号：US20240324201A1
公开(公告)日：2024-09-26
申请号：US18441645
申请日：2024-02-14
发明人： Kang Lib KIM , Seahoon LEE , Junhee LIM
摘要： A semiconductor memory device includes a substrate, a plurality of gate stack structures on the substrate that include a plurality of gate lines stacked and a plurality of insulating films between the plurality of gate lines, a plurality of first separation insulating films that are alternately stacked with the plurality of gate lines, where the plurality of gate stack structures and the plurality of first separation insulating films define a contact hole, a contact electrode that is in the contact hole and contacts the plurality of gate stack structures, and one or more second separation insulating film that is on an uppermost gate line of one or more of the plurality of gate stack structures and separates the contact electrode from the uppermost gate line.
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公开(公告)号：US20240206182A1
公开(公告)日：2024-06-20
申请号：US18523033
申请日：2023-11-29
发明人： Changmin CHOI , Ryoongbin LEE , Dongjin LEE , Junhee LIM
摘要： A non-volatile memory device including a memory cell array including a plurality of word lines stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, and a common source line below the plurality of word lines, a plurality, of driving signal lines connected to a row decoder, and a plurality of pass transistor arrays each including a plurality of vertical pass transistors respectively connected the plurality of driving signal lines and the plurality of word lines, wherein each of the plurality of pass transistor arrays further include an active region including a drain to which at least two of the plurality of vertical pass transistors are simultaneously bonded, and a main contact applying a signal to the active region.
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公开(公告)号：US20230049653A1
公开(公告)日：2023-02-16
申请号：US17722672
申请日：2022-04-18
发明人： Kyunghwan LEE , Yongseok KIM , Dongsoo WOO , Junhee LIM
IPC分类号： H01L23/535 , H01L25/065 , H01L25/18 , H01L23/00 , H01L27/11556 , H01L27/11582
摘要： A semiconductor device including a substrate including a cell array region and a connection region, an electrode structure stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region, Vertical patterns penetrating the electrode structure, a cell contact on the connection region and connected to the pad portion, an insulating pillar below the cell contact, with the pad portion interposed therebetween may be provided. The pad portion may include a first portion having a top surface higher than the line portion, and a second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar.
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公开(公告)号：US20190341456A1
公开(公告)日：2019-11-07
申请号：US16515412
申请日：2019-07-18
发明人： Moorym CHOI , Bongyong LEE , Junhee LIM
IPC分类号： H01L29/10 , H01L29/78 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.
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公开(公告)号：US20240179899A1
公开(公告)日：2024-05-30
申请号：US18514158
申请日：2023-11-20
发明人： Hakseon KIM , Nakjin SON , Dongjin LEE , Junhee LIM , Seongsu KIM , Hanmin CHO , Chiwoong HAM
IPC分类号： H10B41/41 , G11C16/04 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40
CPC分类号： H10B41/41 , G11C16/0483 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40
摘要： A NAND flash device may include a peripheral circuit including a transistor, a substrate, and a device isolation region defining an active region of the substrate. The transistor may include a first gate structure on the active region. The transistor may include source and drain regions extending in a first direction in the active region on both sides of the first gate structure, which may include a first lightly-doped source and drain region adjacent to the first gate structure and a second lightly-doped source and drain region integrally connected thereto. The second lightly-doped source and drain region may be arranged farther from the first gate structure than the first lightly-doped source and drain region. The second lightly-doped source and drain region may have a smaller width in the second direction than a width of the first lightly-doped source and drain region in the second direction.
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公开(公告)号：US20220406808A1
公开(公告)日：2022-12-22
申请号：US17724002
申请日：2022-04-19
发明人： Dongjin LEE , Junhee LIM , Hakseon KIM , Nakjin SON , Jeongeun KIM , Juseong MIN , Changheon LEE
IPC分类号： H01L27/11573 , H01L27/11556 , H01L27/11529 , H01L27/11582
摘要： A semiconductor device includes a lower level layer including a peripheral circuit; and an upper level layer provided on the lower level layer, the upper level layer including a vertically-extended memory cell string, wherein the lower level layer includes a first substrate; a device isolation layer defining a first active region of the first substrate; and a first gate structure including a first gate insulating pattern, a first conductive pattern, a first metal pattern, and a first capping pattern, which are sequentially stacked on the first active region, wherein the first conductive pattern comprises a doped semiconductor material, and the device isolation layer covers a first side surface of the first conductive pattern, and the first metal pattern includes a first body portion on the first conductive pattern.
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