METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

    公开(公告)号:US20230209825A1

    公开(公告)日:2023-06-29

    申请号:US18047109

    申请日:2022-10-17

    CPC classification number: H10B43/27 H10B43/35

    Abstract: Provided is a method of manufacturing a semiconductor device, the method including: forming a mold structure comprising insulation layers and sacrificial layers alternately and repeatedly stacked on a substrate; forming a channel hole extending through the mold structure; forming a blocking layer in the channel hole; forming a charge storage layer on the blocking layer; forming a tunnel insulation layer including a doping element on the charge storage layer; performing heat treatment to diffuse the doping element from the tunnel insulation layer to the charge storage layer; and forming a channel layer on the tunnel insulation layer.

    Semiconductor device
    2.
    发明授权

    公开(公告)号:US12213304B2

    公开(公告)日:2025-01-28

    申请号:US17825441

    申请日:2022-05-26

    Abstract: A semiconductor device includes: a substrate; a conductive line extending on the substrate in a first horizontal direction; an isolation insulating layer extending on the substrate and the conductive line in a second horizontal direction intersecting with the first horizontal direction, and defining a channel trench extending through the isolation insulating layer from an upper surface of the isolation insulating layer to a lower surface of the isolation insulating layer; a crystalline oxide semiconductor layer extending along at least a portion of an inner side surface of the channel trench and at least a portion of a bottom surface of the channel trench and coming in contact with the conductive line; and a gate electrode extending on the crystalline oxide semiconductor layer inside the channel trench in the second horizontal direction.

    SEMICONDUCTOR DEVICE INCLUDING SPACER STRUCTURE HAVING AIR GAP

    公开(公告)号:US20240215225A1

    公开(公告)日:2024-06-27

    申请号:US18391835

    申请日:2023-12-21

    CPC classification number: H10B12/482 H01L21/764 H10B12/0335 H10B12/315

    Abstract: A semiconductor device includes a line structure on the lower structure and including a conductive pattern and an insulating capping pattern on the conductive pattern, a contact structure including a lower portion adjacent to a side surface of the line structure and an upper portion on the lower portion, a spacer structure between a side surface of the lower portion of the contact structure and the side surface of the line structure, an insulating separation pattern on the spacer structure, and a protective layer between the upper portion of the contact structure and the insulating separation pattern. The spacer structure includes an internal spacer, an external spacer, and an air gap between the internal spacer and the external spacer. Regions of the internal spacer and the external spacer exposed by the air gap include an oxide. The insulating separation pattern seals at least a portion of an upper portion of the air gap.

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