公开(公告)号：US12193235B2

公开(公告)日：2025-01-07

申请号：US17537984

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek Oh ,  Hyeyoung Kwon ,  Taein Kim ,  Gukhyon Yon ,  Minhyun Lee

IPC: H10B43/27

Abstract: A nonvolatile memory device includes a channel layer, a plurality of gate electrodes and a plurality of separation layers spaced apart from the channel layer and alternately arranged, a charge trap layer between the gate electrodes in the channel layer, and a charge blocking layer between the charge trap layer and the gate electrode.

公开(公告)号：US20230209825A1

公开(公告)日：2023-06-29

申请号：US18047109

申请日：2022-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minkyung Kang ,  Suhyeong Lee ,  Seohee Park ,  Gukhyon Yon ,  Yongsuk Tak

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: Provided is a method of manufacturing a semiconductor device, the method including: forming a mold structure comprising insulation layers and sacrificial layers alternately and repeatedly stacked on a substrate; forming a channel hole extending through the mold structure; forming a blocking layer in the channel hole; forming a charge storage layer on the blocking layer; forming a tunnel insulation layer including a doping element on the charge storage layer; performing heat treatment to diffuse the doping element from the tunnel insulation layer to the charge storage layer; and forming a channel layer on the tunnel insulation layer.

公开(公告)号：US20240221832A1

公开(公告)日：2024-07-04

申请号：US18328192

申请日：2023-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Kyunghun Kim ,  Sunho Kim ,  Hyungyung Kim ,  Seungyeul Yang ,  Gukhyon Yon ,  Minhyun Lee ,  Joonsuk Lee ,  Seokhoon Choi ,  Hoseok Heo

IPC: G11C16/04 ,  H01L29/16 ,  H01L29/18 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/1606 ,  H01L29/18 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes: a channel layer; a plurality of gate electrodes and a plurality of insulating layers being spaced apart from the channel layer and being alternately arranged; a charge trap layer between the channel layer and a gate electrode, and a charge tunneling layer between the channel layer and the charge trap layer.

公开(公告)号：US11967623B2

公开(公告)日：2024-04-23

申请号：US17388233

申请日：2021-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Jung-Hwan Kim ,  Gukhyon Yon

IPC: H01L29/423 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/42344 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/0657 ,  H01L29/42328 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Disclosed is a semiconductor device comprising gate stack structures on a substrate, separation structures extending in a first direction on the substrate and separating the gate stack structures, and vertical structures penetrating the gate stack structures. Each gate stack structure includes cell dielectric layers and electrodes including upper electrodes, a barrier layer extending between the electrodes and the cell dielectric layers, a separation dielectric pattern extending in the first direction and penetrating the upper electrodes to separate each upper electrode into pieces that are spaced apart from each other in a second direction intersecting the first direction, and capping patterns between the separation dielectric pattern and the upper electrodes. The capping patterns are on sidewalls of each upper electrode and spaced apart from each other in a third direction perpendicular to a top surface of the substrate. Each capping pattern is on a sidewall of the barrier layer.

公开(公告)号：US20220181458A1

公开(公告)日：2022-06-09

申请号：US17388233

申请日：2021-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Jung-Hwan Kim ,  Gukhyon Yon

IPC: H01L29/423 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/48

Abstract: Disclosed is a semiconductor device comprising gate stack structures on a substrate, separation structures extending in a first direction on the substrate and separating the gate stack structures, and vertical structures penetrating the gate stack structures. Each gate stack structure includes cell dielectric layers and electrodes including upper electrodes, a barrier layer extending between the electrodes and the cell dielectric layers, a separation dielectric pattern extending in the first direction and penetrating the upper electrodes to separate each upper electrode into pieces that are spaced apart from each other in a second direction intersecting the first direction, and capping patterns between the separation dielectric pattern and the upper electrodes. The capping patterns are on sidewalls of each upper electrode and spaced apart from each other in a third direction perpendicular to a top surface of the substrate. Each capping pattern is on a sidewall of the barrier layer.

公开(公告)号：US20180261626A1

公开(公告)日：2018-09-13

申请号：US15975861

申请日：2018-05-10

Applicant: Samsung Electronics Co. Ltd.

Inventor： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul yoo

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/24 ,  H01L27/11556 ,  H01L45/00

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

公开(公告)号：US11352698B2

公开(公告)日：2022-06-07

申请号：US16590975

申请日：2019-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangyub Ie ,  Gukhyon Yon

IPC: C23C16/455 ,  H01L21/02 ,  H01L21/687 ,  C23C16/52 ,  C23C16/48

Abstract: An atomic layer deposition (ALD) apparatus includes a light source disposed at an upper portion of a section, a wafer supporting part disposed at a lower portion of the section, and a lens pocket between the light source and the wafer supporting part, and including a frame part and a transparent panel, the lens pocket including a pocket space having sides defined by the frame part and a bottom defined by the transparent panel.

公开(公告)号：US10658375B2

公开(公告)日：2020-05-19

申请号：US15975861

申请日：2018-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul Yoo

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/24 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11575 ,  H01L45/00

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.