公开(公告)号：US20200027925A1

公开(公告)日：2020-01-23

申请号：US16354545

申请日：2019-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNG-HO EUN ,  Daehwan Kang ,  Sungwon Kim ,  Youngbae Kim ,  Seokjae Won

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines. A plurality of first non-volatile memory cells can be on the first side of the plurality of first conductive lines and each can be coupled to the second conductive line and to a respective one of the plurality of first conductive lines, where each of the plurality of first non-volatile memory cells can include a switching element, a variable resistance element, and an electrode arranged in a first sequence. A plurality of second non-volatile memory cells can be on the second side of the plurality of first conductive lines and each can be coupled to the third conductive line and to a respective one of the plurality of first conductive lines, wherein each of the plurality of second non-volatile memory cells includes a switching element, a variable resistance element, and an electrode that are arranged in a second sequence, wherein the first sequence and the second sequence are symmetrical with one another about the plurality of first conductive lines.

公开(公告)号：US20240324184A1

公开(公告)日：2024-09-26

申请号：US18504226

申请日：2023-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokjae Won ,  Yoongoo Kang ,  Jaehong Park

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/315

Abstract: A semiconductor device may include a device isolation part on a substrate, the device isolation part defining a first active portion and a second active portion, with a center portion of the first active portion adjacent in a first direction to an edge portion of the second active portion, A first impurity region may be in the center portion of the first active portion, and a second impurity region may be in the edge portion of the second active portion. A first bit line may be in direct contact with the first impurity region and may extend across the substrate in a second direction that intersects the first direction. A storage node contact may be in contact with the second impurity region, with an upper sidewall and a lower sidewall of the storage node contact on a common side of the storage node contact not vertically aligned with each other.

公开(公告)号：US10971548B2

公开(公告)日：2021-04-06

申请号：US16354545

申请日：2019-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho Eun ,  Daehwan Kang ,  Sungwon Kim ,  Youngbae Kim ,  Seokjae Won

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines. A plurality of first non-volatile memory cells can be on the first side of the plurality of first conductive lines and each can be coupled to the second conductive line and to a respective one of the plurality of first conductive lines, where each of the plurality of first non-volatile memory cells can include a switching element, a variable resistance element, and an electrode arranged in a first sequence. A plurality of second non-volatile memory cells can be on the second side of the plurality of first conductive lines and each can be coupled to the third conductive line and to a respective one of the plurality of first conductive lines, wherein each of the plurality of second non-volatile memory cells includes a switching element, a variable resistance element, and an electrode that are arranged in a second sequence, wherein the first sequence and the second sequence are symmetrical with one another about the plurality of first conductive lines.