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    VARIABLE RESISTANCE MEMORY DEVICE INCLUDING SYMMETRICAL MEMORY CELL ARRANGEMENTS AND METHOD OF FORMING THE SAME
    1.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE INCLUDING SYMMETRICAL MEMORY CELL ARRANGEMENTS AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20200027925A1

    公开(公告)日：2020-01-23

    申请号：US16354545

    申请日：2019-03-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SUNG-HO EUN ,  Daehwan Kang ,  Sungwon Kim ,  Youngbae Kim ,  Seokjae Won

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines. A plurality of first non-volatile memory cells can be on the first side of the plurality of first conductive lines and each can be coupled to the second conductive line and to a respective one of the plurality of first conductive lines, where each of the plurality of first non-volatile memory cells can include a switching element, a variable resistance element, and an electrode arranged in a first sequence. A plurality of second non-volatile memory cells can be on the second side of the plurality of first conductive lines and each can be coupled to the third conductive line and to a respective one of the plurality of first conductive lines, wherein each of the plurality of second non-volatile memory cells includes a switching element, a variable resistance element, and an electrode that are arranged in a second sequence, wherein the first sequence and the second sequence are symmetrical with one another about the plurality of first conductive lines.

    Resistive memory device
    2.
    发明授权
    Resistive memory device 有权

    公开(公告)号：US12029048B2

    公开(公告)日：2024-07-02

    申请号：US17526262

    申请日：2021-11-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunmog Park ,  Jungyu Lee ,  Daehwan Kang ,  Sungho Eun

    IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00

    CPC classification number: H10B63/84 ,  G11C13/0023 ,  H10N70/011 ,  H10N70/882

    Abstract: A resistive memory device includes: memory cells overlapping one another in a vertical direction within a cell array region and each including a switching element and a variable resistive element; first conductive lines each being connected to the switching element; a second conductive line connected to the variable resistive element and conductive pads arranged in a connection region and connected to respective one ends of the first conductive lines, respectively, and having different lengths in the second horizontal direction. A lower conductive pad from among the conductive pads includes a first portion covered by an upper conductive pad, and a second portion not covered by the upper conductive pad, and a thickness of each of the first and second portions in the vertical direction is greater than a thickness of each of the first conductive lines in the vertical direction.

    VARIABLE RESISTANCE MEMORY DEVICE AND A VARIABLE RESISTANCE MEMORY SYSTEM INCLUDING THE SAME
    3.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE AND A VARIABLE RESISTANCE MEMORY SYSTEM INCLUDING THE SAME 有权
    可变电阻存储器件和包括其的可变电阻存储器系统

    公开(公告)号：US20150043267A1

    公开(公告)日：2015-02-12

    申请号：US14257391

    申请日：2014-04-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung-chang Ryoo ,  Hongsik Jeong ,  Daehwan Kang ,  JaeHee Oh ,  Jihyung Yu

    IPC: G11C13/00 ,  H01L27/24

    CPC classification number: G11C13/0004 ,  G11C13/0007 ,  G11C14/00 ,  G11C2213/32 ,  G11C2213/72 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/165

    Abstract: A variable resistance memory system includes a variable resistance memory device including a memory cell array including first and second areas; and a memory controller configured to control the variable resistance memory device. The first area includes first variable resistance memory cells including a first variable resistance material layer and the second area includes second variable resistance memory cells including a second variable resistance material layer having a metallic doping concentration higher than a metallic doping concentration of the first variable resistance material layer. The first variable resistance memory cells are used as storage and the second variable resistance memory cells are used as a buffer memory.

    Abstract translation: 可变电阻存储器系统包括可变电阻存储器件，其包括包括第一和第二区域的存储单元阵列; 以及被配置为控制可变电阻存储器件的存储器控​​制器。 第一区域包括包括第一可变电阻材料层的第一可变电阻存储单元，并且第二区域包括第二可变电阻存储单元，其包括金属掺杂浓度高于第一可变电阻材料的金属掺杂浓度的第二可变电阻材料层 层。 第一可变电阻存储单元用作存储器，第二可变电阻存储单元用作缓冲存储器。

    Three-dimensional semiconductor memory devices
    6.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US11950517B2

    公开(公告)日：2024-04-02

    申请号：US17143493

    申请日：2021-01-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ilmok Park ,  Kyusul Park ,  Daehwan Kang

    IPC: H10N70/00 ,  H10B63/00

    CPC classification number: H10N70/068 ,  H10B63/00 ,  H10N70/063 ,  H10N70/066 ,  H10N70/841

    Abstract: A three-dimensional semiconductor memory device may include a first conductive line extending in a first direction, a second conductive line extending in a second direction crossing the first direction, a cell stack at an intersection of the first and second conductive lines, and a gapfill insulating pattern covering a side surface of the cell stack. The cell stack may include first, second, and third electrodes sequentially stacked, a switching pattern between the first and second electrodes, and a variable resistance pattern between the second and third electrodes. A top surface of the gapfill insulating pattern may be located between top and bottom surfaces of the third electrode.

    Variable resistance memory device including symmetrical memory cell arrangements and method of forming the same
    7.
    发明授权
    Variable resistance memory device including symmetrical memory cell arrangements and method of forming the same 有权

    公开(公告)号：US10971548B2

    公开(公告)日：2021-04-06

    申请号：US16354545

    申请日：2019-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Ho Eun ,  Daehwan Kang ,  Sungwon Kim ,  Youngbae Kim ,  Seokjae Won

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines. A plurality of first non-volatile memory cells can be on the first side of the plurality of first conductive lines and each can be coupled to the second conductive line and to a respective one of the plurality of first conductive lines, where each of the plurality of first non-volatile memory cells can include a switching element, a variable resistance element, and an electrode arranged in a first sequence. A plurality of second non-volatile memory cells can be on the second side of the plurality of first conductive lines and each can be coupled to the third conductive line and to a respective one of the plurality of first conductive lines, wherein each of the plurality of second non-volatile memory cells includes a switching element, a variable resistance element, and an electrode that are arranged in a second sequence, wherein the first sequence and the second sequence are symmetrical with one another about the plurality of first conductive lines.

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