公开(公告)号：US09859288B2

公开(公告)日：2018-01-02

申请号：US14700404

申请日：2015-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Woo Oh ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

IPC: H01L21/764 ,  H01L27/115 ,  H01L21/28 ,  H01L21/762 ,  H01L27/11517 ,  H01L29/06 ,  H01L29/788

CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0653

Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

公开(公告)号：US10727025B2

公开(公告)日：2020-07-28

申请号：US16257895

申请日：2019-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Bo Shim ,  Il-Gyou Shin ,  Seon-Young Lee ,  Alexander Schmidt ,  Shin-Wook Yi

IPC: H01J37/26 ,  G01N23/20058

Abstract: A system of analyzing a crystal defect includes an image processor, an image generator, and a comparator. The image processor processes a measured transmission electron microscope (TEM) image that is provided by capturing an image of a specimen having a crystal structure, to provide structural defect information of the specimen. The image generator provides a plurality of virtual TEM images corresponding to a plurality of three-dimensional structural defects of the crystal structure. The comparator compares the measured TEM image with the plurality of virtual TEM images using the structural defect information to determine a defect type of the measured TEM image.

公开(公告)号：US20200020506A1

公开(公告)日：2020-01-16

申请号：US16257895

申请日：2019-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Bo Shim ,  Il-Gyou Shin ,  Seon-Young Lee ,  Alexander Schmidt ,  Shin-Wook Yi

IPC: H01J37/26 ,  G01N23/20058

Abstract: A system of analyzing a crystal defect includes an image processor, an image generator, and a comparator. The image processor processes a measured transmission electron microscope (TEM) image that is provided by capturing an image of a specimen having a crystal structure, to provide structural defect information of the specimen. The image generator provides a plurality of virtual TEM images corresponding to a plurality of three-dimensional structural defects of the crystal structure. The comparator compares the measured TEM image with the plurality of virtual TEM images using the structural defect information to determine a defect type of the measured TEM image.

公开(公告)号：US20150236028A1

公开(公告)日：2015-08-20

申请号：US14700404

申请日：2015-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Woo OH ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06 ,  H01L21/764

CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0653

Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

Abstract translation: 一种半导体器件，包括其中形成有沟槽的衬底，多个栅极结构，隔离层图案和绝缘层间图案。 衬底包括由沟槽限定的多个有源区，并在第二方向彼此间隔开。 每个有源区域沿着基本上垂直于第二方向的第一方向延伸。 多个栅极结构中的每一个包括依次层叠在基板上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。 隔离层图案形成在沟槽中。 第一隔离层图案在至少一对相邻的浮置栅极的侧壁之间具有至少一个第一气隙。 绝缘层间图案形成在栅极结构之间，第一绝缘层间图案沿第二方向延伸。