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    Method for fabricating semiconductor device
    1.
    发明授权
    Method for fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09466703B2

    公开(公告)日：2016-10-11

    申请号：US14587411

    申请日：2014-12-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-Hyun Song ,  Nak-Jin Son ,  Kwang-Seok Lee ,  Chang-Wook Jeong ,  Ui-Hui Kwon ,  Dong-Won Kim ,  Young-Kwan Park ,  Keun-Ho Lee

    IPC: H01L29/66 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/8234

    CPC classification number: H01L29/66803 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/6681 ,  H01L29/7848

    Abstract: Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region in each of the third and fourth fins by doping impurities into the first to fourth fins on both sides of the first to fourth dummy gate structures by performing an ion implantation process simultaneously in the first and second regions; and removing the first doped region of the first fin and the second doped region of the third fin, or removing the first doped region of the second fin and the second doped region of the fourth fin.

    Abstract translation: 提供一种制造半导体器件的方法。制造方法包括提供包括第一区域和第二区域的衬底，第一区域包括第一和第二子区域，第二区域包括第三和第四子区域，形成 在第一和第二区域上的第一至第四鳍片从基板突出，第一鳍片形成在第一子区域上，第二鳍片形成在第二子区域上，第三鳍片形成在第三子区域上， 并且所述第四鳍形成在所述第四子区域上，形成第一至第四虚拟栅极结构以与所述第一至第四鳍相交，所述第一伪栅极结构形成在所述第一鳍上，所述第二伪栅极结构形成在 第二鳍状物，第三伪栅极结构形成在第三鳍片上，第四伪栅极结构形成在第四鳍片上，在第一鳍片和第二鳍片中的每一个中形成第一掺杂区域 通过在第一和第二区域中同时进行离子注入工艺，通过在第一至第四虚拟栅极结构的两侧上将杂质掺杂到第一至第四鳍中，从而在第三和第四鳍片的每一个中掺杂第二掺杂区域; 以及去除第三鳍片的第一鳍片和第二掺杂区域的第一掺杂区域，或去除第四鳍片的第二鳍片和第二掺杂区域的第一掺杂区域。

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150236028A1

    公开(公告)日：2015-08-20

    申请号：US14700404

    申请日：2015-04-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Woo OH ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

    IPC: H01L27/115 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06 ,  H01L21/764

    CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0653

    Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

    Abstract translation: 一种半导体器件，包括其中形成有沟槽的衬底，多个栅极结构，隔离层图案和绝缘层间图案。 衬底包括由沟槽限定的多个有源区，并在第二方向彼此间隔开。 每个有源区域沿着基本上垂直于第二方向的第一方向延伸。 多个栅极结构中的每一个包括依次层叠在基板上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。 隔离层图案形成在沟槽中。 第一隔离层图案在至少一对相邻的浮置栅极的侧壁之间具有至少一个第一气隙。 绝缘层间图案形成在栅极结构之间，第一绝缘层间图案沿第二方向延伸。

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