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公开(公告)号:US20190267494A1
公开(公告)日:2019-08-29
申请号:US16254842
申请日:2019-01-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jin Bum KIM , Hyoung Sub KIM , Seong Heum CHOI , Jin Yong KIM , Tae Jin PARK , Seung Hun LEE
IPC: H01L29/786 , H01L29/06 , H01L29/423 , H01L21/02 , H01L21/30 , H01L29/66
Abstract: A semiconductor device includes a gate electrode extending in a first direction on a substrate, a first active pattern extending in a second direction intersecting the first direction on the substrate to penetrate the gate electrode, the first active pattern including germanium, an epitaxial pattern on a side wall of the gate electrode, a first semiconductor oxide layer between the first active pattern and the gate electrode, and including a first semiconductor material, and a second semiconductor oxide layer between the gate electrode and the epitaxial pattern, and including a second semiconductor material. A concentration of germanium of the first semiconductor material may be less than a concentration of germanium of the first active pattern, and the concentration of germanium of the first semiconductor material may be different from a concentration of germanium of the second semiconductor material.
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公开(公告)号:US20250072096A1
公开(公告)日:2025-02-27
申请号:US18606375
申请日:2024-03-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Gi Woong SHIM , Seong Heum CHOI , Do Sun LEE , Hyo Seok CHOI , Rak Hwan KIM , Chung Hwan SHIN
IPC: H01L21/8234 , H01L21/308 , H01L21/768 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: A method of fabricating a semiconductor device includes: forming an active pattern on a substrate, forming a source/drain pattern on the active pattern, forming a contact hole on the source/drain pattern, forming a contact barrier layer, which has an upper surface of a first height based on a bottom surface of the contact hole, in the contact hole, forming a passivation layer on the contact barrier layer in the contact hole, forming a mask layer on the passivation layer in the contact hole, removing an upper portion of the contact barrier layer so that an upper surface of the contact barrier layer has a second height lower than the first height, removing the passivation layer and the mask layer, and forming a contact filling layer, which covers the upper surface of the contact barrier layer and fills the contact hole, in the contact hole.
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公开(公告)号:US20240405090A1
公开(公告)日:2024-12-05
申请号:US18390782
申请日:2023-12-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seong Heum CHOI , Jeong Hoon SEO , Rak Hwan KIM , Chung Hwan SHIN , Do Sun LEE
IPC: H01L29/45 , H01L21/285 , H01L29/40
Abstract: A semiconductor device is provided. The semiconductor device includes: a semiconductor device including: an active pattern extending in a first direction; a gate structure including a gate electrode extending in a second direction and a gate spacer on the active pattern, wherein the gate electrode and the gate spacer are spaced apart from each other in the first direction; a source/drain pattern on the active pattern; a contact barrier layer on the source/drain pattern; and a contact filling layer on the contact barrier layer. An uppermost point of the contact barrier layer is between an upper surface of the contact filling layer and a lower surface of the contact filling layer, and outer walls of the contact barrier layer and outer walls of the contact filling layer extend along a common plane.
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公开(公告)号:US20240332381A1
公开(公告)日:2024-10-03
申请号:US18382395
申请日:2023-10-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ji Won KANG , Chung Hwan SHIN , Seong Heum CHOI , Rak Hwan KIM
IPC: H01L29/417 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/45 , H01L29/775 , H01L29/78
CPC classification number: H01L29/41791 , H01L29/0673 , H01L29/401 , H01L29/41733 , H01L29/42392 , H01L29/45 , H01L29/775 , H01L29/7851
Abstract: A semiconductor device may include an active pattern extending in a first direction, a gate structure which is placed on the active pattern to be spaced apart from each other in the first direction, and includes a gate electrode and a gate spacer, the gate electrode extending in a second direction intersecting the first direction, a gate contact on the gate structure, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a via plug on the source/drain contact. An upper surface of the gate contact and a second upper surface of the via plug may be placed on the same plane. A lower surface of the gate contact and a lower surface of the via plug may be different in height, on the basis of an upper surface of the active pattern.
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