公开(公告)号：US20190244944A1

公开(公告)日：2019-08-08

申请号：US16137743

申请日：2018-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonggwan LEE ,  Chul PARK

IPC: H01L25/18 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1434

Abstract: A semiconductor package including a substrate including an external terminal; a first semiconductor chip on the substrate and having a first and a second region; at least one second semiconductor chip on the second region of the first semiconductor chip, the at least one second semiconductor chip exposing a top surface of the first region of the first semiconductor chip; and at least one third semiconductor chip on the at least one second semiconductor chip, wherein the first semiconductor chip includes a first pad electrically connected to the at least one second semiconductor chip; a second pad electrically connected to the at least one third semiconductor chip; and a third pad electrically connected to the external terminal, the first pad is on the top surface of the first region, and at least one of the second pad and the third pad is on a top surface of the second region.