公开(公告)号：US09583440B2

公开(公告)日：2017-02-28

申请号：US14792979

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekjung Kim ,  Myung-Ho Kong ,  Heesook Park ,  Youngwook Park ,  Mansug Kang ,  Seonghwee Cheong

IPC: H01L23/48 ,  H01L23/532 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L23/528 ,  H01L27/22 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L23/53266 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/10817 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/228 ,  H01L28/91 ,  H01L29/0642 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device can include a first conductive line crossing over a field isolation region and crossing over an active region of the device, where the first conductive line can include a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and can be configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern.

Abstract translation: 半导体存储器件可以包括在场隔离区域上交叉并穿过器件的有源区的第一导线，其中第一导线可以包括被掺杂的第一导电图案，第二导电图案和金属硅 在第一和第二导电图案之间的氮化物图案，并且可以被配置为在金属 - 氮化硅图案的下边界处提供与第一导电图案的接触，并且被配置为在金属 - 氮化硅图案的上边界处提供扩散阻挡层， 具有第二导电图案的氮化硅图案。

公开(公告)号：US08883596B2

公开(公告)日：2014-11-11

申请号：US13790076

申请日：2013-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonghwee Cheong ,  Mansug Kang ,  Joon Kim ,  Kihong Nam ,  Gyuwan Choi

IPC: H01L29/66 ,  H01L27/108 ,  H01L27/105 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L29/66666 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/228 ,  H01L27/2454

Abstract: A semiconductor device with vertical channel transistors and a method of fabricating the same are provided. A method of fabricating the semiconductor device includes patterning a substrate to form a trench that defines an active region, forming a sacrificial pattern in a lower region of the trench, forming a spacer on an upper sidewall of the trench, recessing a top surface of the sacrificial pattern to form a window exposing a sidewall of the active region between the spacer and the sacrificial pattern, doping a sidewall of the trench through the window to form a doped region in the active region, and forming a wiring in the trench to be connected to the doped region.

Abstract translation: 提供了具有垂直沟道晶体管的半导体器件及其制造方法。 一种制造半导体器件的方法包括图案化衬底以形成限定有源区的沟槽，在沟槽的下部区域中形成牺牲图案，在沟槽的上侧壁上形成间隔物，使沟槽的顶面凹陷 牺牲图案以形成暴露间隔物和牺牲图案之间的有源区域的侧壁的窗口，通过窗口掺杂沟槽的侧壁以在有源区域中形成掺杂区域，以及在待连接的沟槽中形成布线 到掺杂区域。