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    Semiconductor memory devices including support patterns
    1.
    发明授权
    Semiconductor memory devices including support patterns 有权
    半导体存储器件包括支持图案

    公开(公告)号：US09147685B2

    公开(公告)日：2015-09-29

    申请号：US14475844

    申请日：2014-09-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungmun Byun ,  Hyongsoo Kim ,  Mansug Kang ,  Eunkee Hong

    IPC: H01L27/108 ,  H01L49/02

    CPC classification number: H01L27/10808 ,  H01L27/10852 ,  H01L28/90

    Abstract: A capacitor dielectric can be between the storage node and the electrode layer. A supporting pattern can be connected to the storage node, where the supporting pattern can include at least one first pattern and at least one second pattern layered on one another, where the first pattern can include a material having an etch selectivity with respect to the second pattern.

    Abstract translation: 电容器电介质可以在存储节点和电极层之间。 支撑图案可以连接到存储节点，其中支撑图案可以包括至少一个第一图案和彼此分层的至少一个第二图案，其中第一图案可以包括具有相对于第二图案的蚀刻选择性的材料 模式。

    INTEGRATED CIRCUIT DEVICES WITH CAPACITOR AND METHODS OF MANUFACTURING THE SAME
    3.
    发明申请
    INTEGRATED CIRCUIT DEVICES WITH CAPACITOR AND METHODS OF MANUFACTURING THE SAME 有权
    具有电容器的集成电路装置及其制造方法

    公开(公告)号：US20130277802A1

    公开(公告)日：2013-10-24

    申请号：US13790773

    申请日：2013-03-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dongkyun Park ,  Mansug Kang ,  Hyongsoo Kim ,  Sangjun Park ,  Kukhan Yoon

    IPC: H01L49/02

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91 ,  H01L28/92

    Abstract: An integrated circuit device with capacitors and methods of forming the integrated circuit device are provided. The methods may include forming a first lower capacitor electrode pattern on an inner surface of a hole in a mold layer. The first lower capacitor electrode pattern may have a hollow cylindrical shape and an opening in an upper surface. The method may further include forming a second lower capacitor electrode pattern plugging the opening and an upper surface of the second lower capacitor electrode pattern may be planar. The first and the second lower capacitor electrode patterns may comprise a lower capacitor electrode including a void. Additionally, the method may include removing the mold layer to expose the lower capacitor electrode, forming a dielectric layer on the lower capacitor electrode, and forming an upper capacitor electrode layer on the dielectric layer.

    Abstract translation: 提供具有电容器的集成电路器件和形成集成电路器件的方法。 所述方法可以包括在模具层中的孔的内表面上形成第一低电容电极图案。 第一较低电容器电极图案可以具有中空圆柱形形状和在上表面中的开口。 该方法还可以包括形成插入开口的第二下电容器电极图案，并且第二下电容器电极图案的上表面可以是平面的。 第一和第二下部电容器电极图案可以包括包括空隙的下部电容器电极。 此外，该方法可以包括去除模具层以暴露下电容器电极，在下电容器电极上形成电介质层，并在电介质层上形成上电容器电极层。

    Integrated circuit devices with capacitor and methods of manufacturing the same
    5.
    发明授权
    Integrated circuit devices with capacitor and methods of manufacturing the same 有权
    具有电容器的集成电路器件及其制造方法

    公开(公告)号：US09111953B2

    公开(公告)日：2015-08-18

    申请号：US13790773

    申请日：2013-03-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongkyun Park ,  Mansug Kang ,  Hyongsoo Kim ,  Sangjun Park ,  Kukhan Yoon

    IPC: H01L49/02 ,  H01L27/108

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91 ,  H01L28/92

    Abstract: An integrated circuit device with capacitors and methods of forming the integrated circuit device are provided. The methods may include forming a first lower capacitor electrode pattern on an inner surface of a hole in a mold layer. The first lower capacitor electrode pattern may have a hollow cylindrical shape and an opening in an upper surface. The method may further include forming a second lower capacitor electrode pattern plugging the opening and an upper surface of the second lower capacitor electrode pattern may be planar. The first and the second lower capacitor electrode patterns may comprise a lower capacitor electrode including a void. Additionally, the method may include removing the mold layer to expose the lower capacitor electrode, forming a dielectric layer on the lower capacitor electrode, and forming an upper capacitor electrode layer on the dielectric layer.

    Abstract translation: 提供具有电容器的集成电路器件和形成集成电路器件的方法。 所述方法可以包括在模具层中的孔的内表面上形成第一低电容电极图案。 第一较低电容器电极图案可以具有中空圆柱形形状和在上表面中的开口。 该方法还可以包括形成插入开口的第二下电容器电极图案，并且第二下电容器电极图案的上表面可以是平面的。 第一和第二下部电容器电极图案可以包括包括空隙的下部电容器电极。 此外，该方法可以包括去除模具层以暴露下电容器电极，在下电容器电极上形成介电层，并在电介质层上形成上电容器电极层。

    Semiconductor device with vertical channel transistor and method of fabricating the same
    6.
    发明授权
    Semiconductor device with vertical channel transistor and method of fabricating the same 有权
    具有垂直沟道晶体管的半导体器件及其制造方法

    公开(公告)号：US08883596B2

    公开(公告)日：2014-11-11

    申请号：US13790076

    申请日：2013-03-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seonghwee Cheong ,  Mansug Kang ,  Joon Kim ,  Kihong Nam ,  Gyuwan Choi

    IPC: H01L29/66 ,  H01L27/108 ,  H01L27/105 ,  H01L27/22 ,  H01L27/24

    CPC classification number: H01L29/66666 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/228 ,  H01L27/2454

    Abstract: A semiconductor device with vertical channel transistors and a method of fabricating the same are provided. A method of fabricating the semiconductor device includes patterning a substrate to form a trench that defines an active region, forming a sacrificial pattern in a lower region of the trench, forming a spacer on an upper sidewall of the trench, recessing a top surface of the sacrificial pattern to form a window exposing a sidewall of the active region between the spacer and the sacrificial pattern, doping a sidewall of the trench through the window to form a doped region in the active region, and forming a wiring in the trench to be connected to the doped region.

    Abstract translation: 提供了具有垂直沟道晶体管的半导体器件及其制造方法。 一种制造半导体器件的方法包括图案化衬底以形成限定有源区的沟槽，在沟槽的下部区域中形成牺牲图案，在沟槽的上侧壁上形成间隔物，使沟槽的顶面凹陷 牺牲图案以形成暴露间隔物和牺牲图案之间的有源区域的侧壁的窗口，通过窗口掺杂沟槽的侧壁以在有源区域中形成掺杂区域，以及在待连接的沟槽中形成布线 到掺杂区域。

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