公开(公告)号：US20250072064A1

公开(公告)日：2025-02-27

申请号：US18945603

申请日：2024-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyemi LEE ,  Seongjae GO ,  Hyeonjoo SONG ,  Sunjoong PARK ,  Hanyong PARK

IPC: H01L29/06 ,  G11C5/06 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device including a peripheral circuit layer on a substrate; a lower stack and upper stack on the substrate; a stopper layer on the upper stack and including an insulating material; an upper mold layer on the stopper layer; a cell channel structure extending through the layers, a side surface of the cell channel structure contacting the stopper layer; first and second capping layers; a word line separation structure including a protrusion protruding toward the stopper layer; and a bit line contact plug connected to the cell channel structure, wherein an inner side surface of the stopper layer is offset from an inner side surface of the upper stack, and in contact with the word line separation structure.

公开(公告)号：US20250017018A1

公开(公告)日：2025-01-09

申请号：US18640811

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongjae GO ,  Duyoung YANG ,  Kangmin KIM ,  Jongseon AHN ,  Byeongin CHOE

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

Abstract: A semiconductor device includes a plate layer; gate electrodes stacked and spaced apart from each other on the plate layer and including first gate electrodes and a second gate electrode on the first gate electrodes; first channel structures extending in the first gate electrodes; and second channel structures extending in the second gate electrode and electrically connected to the first channel structures, respectively, wherein the second gate electrode includes a metal material, and wherein each of the second channel structures includes a second channel layer, a second gate dielectric layer between the second channel layer and the second gate electrode, a second channel buried insulating layer on an internal side surface of the second channel layer, a second channel pad on the second channel buried insulating layer, and a second pad oxide layer on the second channel pad and the second channel layer.

公开(公告)号：US20220199767A1

公开(公告)日：2022-06-23

申请号：US17468814

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyemi LEE ,  Seongjae GO ,  Hyeonjoo SONG ,  Sunjoong PARK ,  Hanyong PARK

IPC: H01L29/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L25/065

Abstract: A semiconductor device including a peripheral circuit layer on a substrate; a lower stack and upper stack on the substrate; a stopper layer on the upper stack and including an insulating material; an upper mold layer on the stopper layer; a cell channel structure extending through the layers, a side surface of the cell channel structure contacting the stopper layer; first and second capping layers; a word line separation structure including a protrusion protruding toward the stopper layer; and a bit line contact plug connected to the cell channel structure, wherein an inner side surface of the stopper layer is offset from an inner side surface of the upper stack, and in contact with the word line separation structure.

公开(公告)号：US20220139943A1

公开(公告)日：2022-05-05

申请号：US17232763

申请日：2021-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjae GO ,  Jongsoo KIM

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11526 ,  H01L23/528

Abstract: A semiconductor device includes a stack structure including mold layers and horizontal conductive layers, which are alternately stacked. A channel structure vertically extending in the stack structure is provided. A pillar structure vertically extending in the stack structure is provided. A contact plug connected to a corresponding one of the horizontal conductive layers is disposed. The pillar structure includes a pillar extending through the horizontal conductive layers, and extensions protruding from a side surface of the pillar. Each extension is horizontally aligned with a corresponding one of the horizontal conductive layers.