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公开(公告)号：US20220336489A1
公开(公告)日：2022-10-20
申请号：US17529331
申请日：2021-11-18
发明人： Seugmin LEE , Kiyoon KANG , Kangmin KIM , Dongseong KIM , Junhyoung KIM , Byungkwan YOU
IPC分类号： H01L27/11582 , H01L23/00
摘要： A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure disposed on the source structure and including insulating patterns and conductive patterns alternately stacked, a memory channel structure electrically connected to the source structure and penetrating the gate stack structure, a support structure penetrating the gate stack structure and the source structure, and an insulating layer covering the gate stack structure, the memory channel structure and the support structure. The support structure includes an outer support layer contacting side walls of the insulating patterns and side walls of the conductive patterns, and a support pattern and an inner support layer contacting an inner side wall of the outer support layer.
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公开(公告)号：US20220173120A1
公开(公告)日：2022-06-02
申请号：US17465412
申请日：2021-09-02
发明人： Seungmin LEE , Junhyoung KIM , Kangmin KIM , Byungkwan YOU
IPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/1157 , H01L27/11565 , H01L27/11573 , H01L23/522 , H01L23/528
摘要： A semiconductor device includes: a substrate that includes a first region and a second region; gate electrodes stacked on the first region in a first direction, extend by different lengths in a second direction on the second region, and respectively including a pad region having an upper surface that is upwardly exposed in the second region; interlayer insulating layers alternately stacked with the gate electrodes; channel structures that extend in the first direction and penetrate through the gate electrodes; plug insulating layers alternately disposed with the interlayer insulating layers and parallel to the gate electrodes below the pad region; and contact plugs that extend in the first direction and respectively penetrate through the pad region and the plug insulating layers below the pad region. In each of the gate electrodes, the pad region has physical properties that differ from physical properties of regions other than the pad region.
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公开(公告)号：US20220123014A1
公开(公告)日：2022-04-21
申请号：US17338823
申请日：2021-06-04
发明人： Kangmin KIM , Seungmin SONG , Dongseog EUN , Seokhwa JUNG
IPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11529 , H01L27/11573
摘要： A semiconductor chip includes a substrate, a source structure disposed on the substrate, and a support pattern disposed on the source structure. Each of the source structure and the support pattern includes polysilicon. The semiconductor chip further includes an electrode structure disposed on the support pattern, and a plurality of vertical structures extending vertically through the electrode structure. The electrode structure includes a lower electrode structure disposed on the support pattern and including a plurality of lower gate electrodes and a plurality of first insulating films, a second insulating film disposed on the lower electrode structure, and an upper electrode structure disposed on the second insulating film and including a plurality of upper gate electrodes and a plurality of third insulating films. The vertical structures contact the source structure above the source structure.
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公开(公告)号：US20220367513A1
公开(公告)日：2022-11-17
申请号：US17878304
申请日：2022-08-01
发明人： Seungmin SONG , Beyounghyun KOH , Yongjin KWON , Kangmin KIM , Jaehoon SHIN , JoongShik SHIN , Sungsoo AHN , Seunghwan LEE
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L27/1157
摘要： A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.
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公开(公告)号：US20220123001A1
公开(公告)日：2022-04-21
申请号：US17348172
申请日：2021-06-15
发明人： Kangmin KIM , Jaehoon SHIN , Dongseog EUN , Geunwon LIM
IPC分类号： H01L27/11526 , H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573
摘要： A semiconductor device includes a first substrate; devices on the first substrate; a second substrate on the devices; gate electrodes stacked on the second substrate and spaced apart from each other in a first direction; channel structures penetrating the gate electrodes, extending in the first direction, and including a channel layer; isolation regions penetrating the gate electrodes and extending in a second direction; a through contact plug penetrating the second substrate, extending in the first direction, and electrically connecting the gate electrodes to the devices; a barrier structure spaced apart from the through contact plug and surrounding the through contact plug; and a support structure on the gate electrodes and including support patterns, wherein the support structure has first through regions spaced apart from each other in the second direction on the isolation regions and a second through region in contact with an upper surface of the barrier structure.
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公开(公告)号：US20210320125A1
公开(公告)日：2021-10-14
申请号：US17162408
申请日：2021-01-29
发明人： Jaehoon SHIN , Kangmin KIM , Kyeongjin PARK , Seungmin SONG , Joongshik SHIN , Geunwon LIM
IPC分类号： H01L27/11582 , H01L27/11573 , H01L27/11565 , H01L27/11519 , H01L27/11526 , H01L27/11556 , H01L23/522
摘要： A vertical memory device includes a gate electrode structure, a channel, an insulation pattern structure, an etch stop structure, and a through via. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The channel extends in the first direction through the gate electrode structure. The insulation pattern structure extends through the gate electrode structure. The etch stop structure extends through the gate electrode structure and surround at least a portion of a sidewall of the insulation pattern structure, and the etch stop structure includes a filling pattern and an etch stop pattern on a sidewall of the filling pattern. The through via extends in the first direction through the insulation pattern structure.
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公开(公告)号：US20210111188A1
公开(公告)日：2021-04-15
申请号：US16895364
申请日：2020-06-08
发明人： Seungmin SONG , Beyounghyun KOH , Yongjin KWON , Kangmin KIM , Jaehoon SHIN , JoongShik SHIN , Sungsoo AHN , Seunghwan LEE
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11565
摘要： A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.
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