公开(公告)号：US20230385203A1

公开(公告)日：2023-11-30

申请号：US18101352

申请日：2023-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngseok KIM ,  Junbeom JANG ,  Seongmin JO

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009

Abstract: Disclosed is an input output memory management unit (IOMMU) including a first memory device including a translation lookaside buffer (TLB), a second memory device including a translation group table, a plurality of translation request controllers, each of which is configured to perform an address translation operation, and an allocation controller. The allocation controller may be configured to receive a first request including a first page table identifier (ID), a first virtual page number, and a first page offset, looks up the TLB by using the first page table ID and the first virtual page number, look up the translation group table by using the first page table ID and the first virtual page number when a TLB miss for the first request occurs, and allocate a first translation request controller among the plurality of translation request controllers based on a translation group table miss for the first request.

公开(公告)号：US20220179793A1

公开(公告)日：2022-06-09

申请号：US17374076

申请日：2021-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongmin JO ,  Youngseok KIM ,  Chunghwan YOU ,  Wooil KIM

IPC: G06F12/0862 ,  G06F12/10

Abstract: An operating method of a system-on-chip includes outputting a prefetch command in response to an update of mapping information on a first read target address, the update occurring in a first translation lookaside buffer storing first mapping information of a second address with respect to a first address, and storing, in response to the prefetch command, in a second translation lookaside buffer, second mapping information of a third address with respect to at least some second addresses of an address block including a second read target address.

公开(公告)号：US20230269205A1

公开(公告)日：2023-08-24

申请号：US18311181

申请日：2023-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongmin JO ,  Heeseong LEE ,  Jaehyun KIM ,  Jinsu JUNG

IPC: H04L49/90 ,  H04L49/00 ,  H04L49/109

CPC classification number: H04L49/9094 ,  H04L49/3027 ,  H04L49/9021 ,  H04L49/109

Abstract: A Network-on-Chip (NoC) includes a packet transmission switch, and a corresponding method of operating the NoC includes storing packets received from an input terminal in a buffer, storing buffer locations in which each of the packets is stored in an ordering queue of an output terminal, and sequentially outputting the packets from the output terminal according to the buffer locations.

公开(公告)号：US20220224658A1

公开(公告)日：2022-07-14

申请号：US17644720

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongmin JO ,  Heeseong Lee ,  Jaehyun Kim ,  Jinsu Jung

IPC: H04L49/90 ,  H04L49/109 ,  H04L49/00

Abstract: A Network-on-Chip (NoC) includes a packet transmission switch, and a corresponding method of operating the NoC includes storing packets received from an input terminal in a buffer, storing buffer locations in which each of the packets is stored in an ordering queue of an output terminal, and sequentially outputting the packets from the output terminal according to the buffer locations.