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1.发明申请公开(公告)号：US20220224658A1
公开(公告)日：2022-07-14
申请号：US17644720
申请日：2021-12-16
发明人： Seongmin JO , Heeseong Lee , Jaehyun Kim , Jinsu Jung
IPC分类号： H04L49/90 , H04L49/109 , H04L49/00
摘要： A Network-on-Chip (NoC) includes a packet transmission switch, and a corresponding method of operating the NoC includes storing packets received from an input terminal in a buffer, storing buffer locations in which each of the packets is stored in an ordering queue of an output terminal, and sequentially outputting the packets from the output terminal according to the buffer locations.
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2.发明授权公开(公告)号：US12113723B2
公开(公告)日：2024-10-08
申请号：US18311181
申请日：2023-05-02
发明人： Seongmin Jo , Heeseong Lee , Jaehyun Kim , Jinsu Jung
IPC分类号： H04L12/24 , H04L49/00 , H04L49/109 , H04L49/90
CPC分类号： H04L49/9094 , H04L49/109 , H04L49/3027 , H04L49/9021
摘要： A Network-on-Chip (NoC) includes a packet transmission switch, and a corresponding method of operating the NoC includes storing packets received from an input terminal in a buffer, storing buffer locations in which each of the packets is stored in an ordering queue of an output terminal, and sequentially outputting the packets from the output terminal according to the buffer locations.
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3.发明授权公开(公告)号：US11652761B2
公开(公告)日：2023-05-16
申请号：US17644720
申请日：2021-12-16
发明人： Seongmin Jo , Heeseong Lee , Jaehyun Kim , Jinsu Jung
IPC分类号： H04L12/28 , H04L49/90 , H04L49/00 , H04L49/109
CPC分类号： H04L49/9094 , H04L49/109 , H04L49/3027 , H04L49/9021
摘要： A Network-on-Chip (NoC) includes a packet transmission switch, and a corresponding method of operating the NoC includes storing packets received from an input terminal in a buffer, storing buffer locations in which each of the packets is stored in an ordering queue of an output terminal, and sequentially outputting the packets from the output terminal according to the buffer locations.
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公开(公告)号：US09747998B2
公开(公告)日：2017-08-29
申请号：US14462843
申请日：2014-08-19
发明人： Sua Kim , Dongsoo Kang , Chulwoo Park , Jun Hee Yoo , Hak-Soo Yu , Jaeyoun Youn , Sung Hyun Lee , Jinsu Jung , Hyojin Choi
CPC分类号： G11C17/16 , G11C17/18 , G11C29/027 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C2029/4402
摘要： A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.
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