-
公开(公告)号：US11665883B2
公开(公告)日：2023-05-30
申请号：US17202465
申请日：2021-03-16
发明人： Inkyoung Heo , Hyo-Sub Kim , Sohyun Park , Taejin Park , Seung-Heon Lee , Youn-Seok Choi , Sunghee Han , Yoosang Hwang
IPC分类号： H01L27/108 , H01L23/532 , H01L21/768 , H01L23/482 , H01L21/762
CPC分类号： H01L27/10814 , H01L21/7682 , H01L23/5329 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L21/76264 , H01L23/4821
摘要： A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.
-
公开(公告)号：US20230155024A1
公开(公告)日：2023-05-18
申请号：US17969491
申请日：2022-10-19
发明人： Junhyeok Ahn , Sohyun Park
IPC分类号： H01L29/78 , H01L27/088 , H01L29/423
CPC分类号： H01L29/7827 , H01L27/088 , H01L29/4236 , H01L27/108
摘要： A semiconductor device includes a semiconductor substrate provided with active regions, an isolation layer defining each active region on the semiconductor substrate, gate electrodes overlapping the active regions and extending in a first direction parallel to an upper surface of the semiconductor substrate, an insulating barrier structure disposed at a level higher than a level of where the gate electrodes are disposed, the insulating barrier structure having a grid pattern including grid cells, bitlines extending in a second direction perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate, and disposed at a level higher than a level of where the insulating barrier structure is disposed, and first contact plugs, each first contact plug being disposed in a corresponding grid cell of the grid cells of the insulating barrier structure.
-
公开(公告)号：US11037930B2
公开(公告)日：2021-06-15
申请号：US16670232
申请日：2019-10-31
发明人： Taejin Park , Keunnam Kim , Huijung Kim , Sohyun Park , Jaehwan Cho , Yoosang Hwang
IPC分类号： H01L27/108
摘要： A semiconductor device includes a substrate, a bit line structure on the substrate, a contact plug structure being adjacent to the bit line structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a capacitor electrically connected to the contact plug structure. The contact plug structure includes a lower contact plug, a metal silicide pattern, and an upper contact plug that are sequentially stacked on the substrate. The metal silicide pattern has an L-shaped cross section.
-
公开(公告)号：US20240324183A1
公开(公告)日：2024-09-26
申请号：US18489034
申请日：2023-10-18
发明人： Chanhoon Park , Jongkyu Kim , Seunghoon Kim , Sohyun Park , Woohyun Lee
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/02 , H10B12/315 , H10B12/485
摘要： An integrated circuit device includes a substrate having an active area, a plurality of bit line structures on the substrate, the plurality of bit line structures including insulating spacers on sidewalls thereof, a buried contact between the plurality of bit line structures and electrically connected to the active area, an insulation capping pattern on a bit line structure of the plurality of bit line structures, and a landing pad electrically connected to the buried contact, the landing pad arranged to vertically overlap the bit line structure on the insulation capping pattern, wherein an uppermost surface of the landing pad is higher than an uppermost surface of the insulation capping pattern, relative to the substrate.
-
公开(公告)号：US20240160862A1
公开(公告)日：2024-05-16
申请号：US18369584
申请日：2023-09-18
发明人： Joonghoon KIM , Sangha Kim , Jiwan Kim , Sangil Park , Sohyun Park , Taehwan Yoo
IPC分类号： G06F40/58 , G06F40/253
CPC分类号： G06F40/58 , G06F40/253
摘要： An electronic apparatus includes a memory configured to store instructions, and a processor configured to execute the instructions to receive a text of a first language, generate, based on the text of the first language, style information indicating a translation style to be applied to the text of the first language and machine-translate the text of the first language into text of a second language based on the generated style information.
-
6.发明授权公开(公告)号：US11929324B2
公开(公告)日：2024-03-12
申请号：US18133575
申请日：2023-04-12
发明人： Taejin Park , Keunnam Kim , Sohyun Park , Jin-Hwan Chun , Wooyoung Choi , Sunghee Han , Inkyoung Heo , Yoosang Hwang
IPC分类号： H01L23/48 , G11C5/10 , H01L21/768 , H01L23/52 , H01L23/528 , H01L29/06 , H01L29/423 , H10B12/00
CPC分类号： H01L23/528 , G11C5/10 , H01L21/76831 , H01L29/0649 , H01L29/4236 , H10B12/485
摘要： The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.
-
公开(公告)号：US20230145857A1
公开(公告)日：2023-05-11
申请号：US17935119
申请日：2022-09-25
发明人： HYERAN LEE , Sohyun Park , Junhyeok Ahn
IPC分类号： H01L27/108 , G11C5/06
CPC分类号： H01L27/10814 , G11C5/063
摘要： A semiconductor device includes a conductive contact plug disposed on a substrate, a bit line structure disposed on the conductive contact plug, first and second spacers, and a capping pattern disposed on the first and second spacers. The conductive contact plug includes a lower portion that has a first width and an upper portion that has a second width narrower than the first width. The bit line structure includes a conductive structure and an insulation structure stacked in a vertical direction. The first and second spacers are stacked on a sidewall of the lower portion of the conductive contact plug in a horizontal direction. The capping pattern covers a sidewall of the upper portion of the conductive contact plug. The first spacer directly contacts the sidewall of the lower portion of the conductive contact plug and includes air.
-
公开(公告)号：US11600570B2
公开(公告)日：2023-03-07
申请号：US17097337
申请日：2020-11-13
发明人： Hyo-Sub Kim , Sohyun Park , Daewon Kim , Dongoh Kim , Eun A Kim , Chulkwon Park , Taejin Park , Kiseok Lee , Sunghee Han
IPC分类号： H01L23/535 , H01L21/768 , H01L27/108 , H01L23/532
摘要： A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.
-
公开(公告)号：US20230422488A1
公开(公告)日：2023-12-28
申请号：US18192329
申请日：2023-03-29
发明人： Jongmin KIM , Sohyun Park , Chansic Yoon , Dongmin Choi , Seungbo Ko , Hyosub Kim , Jingkuk Bae , Woojin Jeong , Eunkyung Cha , Junhyeok Ahn
IPC分类号： H10B12/00
CPC分类号： H10B12/485 , H10B12/0335 , H10B12/482 , H10B12/315
摘要： A semiconductor device including a first contact plug structure on a substrate, a lower spacer structure on a sidewall of the first contact plug structure, and a bit line structure on the first contact plug structure and including a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate may be provided. The first contact plug structure may include a conductive pad contacting the upper surface of the substrate, an ohmic contact pattern on the conductive pad, and a conductive filling pattern on the ohmic contact pattern. The conductive filling pattern may include metal, and include a lower portion having a relatively large width and an upper portion having a relatively small width. The lower spacer structure may contact a sidewall of the conductive filling pattern.
-
公开(公告)号：US20230189503A1
公开(公告)日：2023-06-15
申请号：US17886652
申请日：2022-08-12
发明人： Sohyun Park , Eunjung Kim
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/10823 , H01L27/10885 , H01L27/10888
摘要： A semiconductor memory device may include a substrate including active regions. Word lines may be on the active regions and may be extended in a first direction. Bit line structures may be on the word lines, and each of the bit line structures may include a contact portion, which is connected to a first impurity region of an active region, and a line portion, which is on the contact portion and which extends in a second direction. Contact plugs may be between the bit line structures and may be connected to respective second impurity regions of the active regions. Connection patterns may connect the contact plugs to the second impurity regions. Each of the connection patterns may include a first concave surface that faces the contact portion and a second convex surface that is opposite to the first surface.
-
-
-
-
-
-
-
-
-
搜索结果
16 条记录 (耗时 0.016 秒)
