公开(公告)号：US08836074B2

公开(公告)日：2014-09-16

申请号：US13728785

申请日：2012-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Kwan You ,  Seung-Woo Paek ,  Chung-Il Hyun ,  Jung-Dal Choi

IPC: H01L29/06 ,  H01L21/28 ,  H01L27/10 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L27/10 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66636

Abstract: A semiconductor memory device includes linear patterns disposed between isolation trenches extending in a first direction in a semiconductor device and having a first crystal direction the same as the semiconductor substrate. A bridge pattern connects at least two adjacent linear patterns and includes a semiconductor material having a second crystal direction different from the first crystal direction. A first isolation layer pattern is disposed in at least one of the isolation trenches in a field region of the semiconductor substrate. Memory cells are disposed on at least one of the linear patterns.

Abstract translation: 半导体存储器件包括设置在半导体器件中沿第一方向延伸并具有与半导体衬底相同的第一晶体方向的隔离沟槽之间的线状图案。 桥模式连接至少两个相邻的线状图案，并且包括具有与第一晶体方向不同的第二晶体方向的半导体材料。 第一隔离层图案设置在半导体衬底的场区域中的至少一个隔离沟槽中。 存储单元被布置在至少一个线性图案上。

公开(公告)号：US09202932B2

公开(公告)日：2015-12-01

申请号：US13834529

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Woo Paek ,  Jung-Dal Choi ,  Young-Seop Rah ,  Byung-Kwan You ,  Seok-Won Lee

IPC: H01L21/3205 ,  H01L29/792 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L21/764 ,  H01L27/115 ,  H01L23/522

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5222 ,  H01L27/11568 ,  H01L29/66833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of manufacturing a semiconductor device, a dielectric layer structure and a control gate layer can be formed sequentially on a substrate. The control gate layer can be partially etched to form a plurality of control gates. A gate spacer and a sacrificial spacer sequentially can be stacked on a sidewall of the control gate and on a portion of the dielectric layer structure. The dielectric layer structure can be partially etched using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns. The sacrificial spacer can be removed. An insulating interlayer can be formed on the substrate to form an air gap. The insulating interlayer can cover the dielectric layer structure pattern, the gate spacer and the control gate. The air gap can extend between the adjacent gate spacers and between the adjacent dielectric layer structure patterns.

Abstract translation: 在制造半导体器件的方法中，可以在衬底上依次形成电介质层结构和控制栅极层。 可以部分蚀刻控制栅极层以形成多个控制栅极。 栅极间隔物和牺牲隔离物可以顺序地堆叠在控制栅极的侧壁上以及电介质层结构的一部分上。 可以使用牺牲间隔物和栅极间隔物作为蚀刻掩模来部分地蚀刻电介质层结构，以形成多个电介质层结构图案。 可以去除牺牲隔离物。 可以在基板上形成绝缘中间层以形成气隙。 绝缘中间层可以覆盖电介质层结构图案，栅极间隔物和控制栅极。 气隙可以在相邻的栅极间隔件之间和相邻的介电层结构图案之间延伸。