公开(公告)号：US20240215250A1

公开(公告)日：2024-06-27

申请号：US18340419

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Jooheon Kang ,  Yumin Kim ,  Garam Park ,  Hyunjae Song ,  Dongho Ahn ,  Seungyeul Yang ,  Myunghun Woo ,  Jinwoo Lee ,  Seungdam Hyun

IPC: H10B43/35 ,  G11C16/04 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device including the vertical stack structure includes a gate electrode, a resistance change layer, a channel between the gate electrode and the resistance change layer, and an island structure between the resistance change layer and the channel and in contact with the resistance change layer and the channel, and a gate insulating layer between the gate electrode and the channel.

公开(公告)号：US20250017017A1

公开(公告)日：2025-01-09

申请号：US18439308

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoseok Heo ,  Kyunghun Kim ,  Sunho Kim ,  Hyungyung Kim ,  Minhyun Lee ,  Seokhoon Choi ,  Seungdam Hyun

IPC: H10B43/35 ,  H01L29/423

Abstract: A vertical NAND flash memory device and an electronic apparatus including the same are provided. The vertical NAND flash memory device includes a plurality of cell arrays. Each of the plurality of cell arrays includes a channel layer, a charge trap layer, and a plurality of gate electrodes provided on the charge trap layer. The charge trap layer includes a matrix including amorphous metal oxynitride and nanocrystals dispersed in the matrix and including nitride having semiconductor characteristics.