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1.
公开(公告)号:US20220385277A1
公开(公告)日:2022-12-01
申请号:US17696086
申请日:2022-03-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seungman LIM , Minsu KIM , Ahreum KIM
IPC: H03K3/037 , H03K17/687
Abstract: An integrated circuit includes a flip-flop configured to operate in synchronization with a clock signal. The flip-flop includes a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, or the multiplexer configured to output an inverted signal of a data input signal or a signal having a first level to a first node based on a reset input signal, a master latch configured to latch the signal output through the first node, and to output the latched signal, and a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.
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公开(公告)号:US20220334182A1
公开(公告)日:2022-10-20
申请号:US17551974
申请日:2021-12-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chunghee KIM , Ahreum KIM , Minsu KIM , Seungman LIM
IPC: G01R31/3185
Abstract: A multi-bit flip-flop includes a first flip-flop having a first output driver connected to a first output pin and arranged on a first row, a second flip-flop including a second output driver electrically connected to a second output pin and arranged on a second row, and an internal hold buffer connected to the first output driver on the first row and the second flip-flop on the second row.
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公开(公告)号:US20220058331A1
公开(公告)日:2022-02-24
申请号:US17360355
申请日:2021-06-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seungman LIM , Hakchul JUNG , Sanghoon BAEK , Jaewoo SEO , Jisu YU , Hyeongyu YOU
IPC: G06F30/3953 , H01L23/528
Abstract: An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.
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