公开(公告)号：US20250056794A1

公开(公告)日：2025-02-13

申请号：US18653191

申请日：2024-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyun Lim ,  Soobin Kim ,  Seungyoung Seo ,  Sunwoo Heo

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral circuit region, a peripheral circuit gate line on the peripheral circuit region of the substrate, an interlayer insulating layer surrounding the peripheral circuit gate line, a contact plug passing through the interlayer insulating layer to be connected to the substrate, a wiring pad on the contact plug, and a metal via being in contact with the wiring pad, wherein a first sidewall and a second sidewall of the contact plug form acute angles with an upper surface of the contact plug, and a first sidewall and a second sidewall of the wiring pad form acute angles with a lower surface of the wiring pad.

公开(公告)号：US20240306376A1

公开(公告)日：2024-09-12

申请号：US18391828

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Sunwoo Heo ,  Soobin Kim ,  Jinsub Kim ,  Seungyoung Seo ,  Taeyong Song

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device includes a substrate including an active region; a cell gate structure disposed in the substrate, crossing the active region, and extending in a first horizontal direction; bitline structures crossing the cell gate structure and extending in a second horizontal direction intersecting the first horizontal direction; a contact plug disposed between the bitline structures; a landing pad structure disposed on the contact plug and including a lower landing pad and an upper landing pad on the lower landing pad, wherein the upper landing pad includes a cavity; a conductive pattern disposed in the cavity of the upper landing pad; and an insulating pattern structure in contact with one of the bitline structures and in contact with the landing pad structure.

公开(公告)号：US20230200054A1

公开(公告)日：2023-06-22

申请号：US18084190

申请日：2022-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieun Lee ,  Dongho Yu ,  Deoksung Hwang ,  Gisung Kim ,  Seungyoung Seo

IPC: H10B12/00 ,  H01L23/528 ,  H01L23/522

CPC classification number: H10B12/315 ,  H10B12/482 ,  H01L23/5283 ,  H01L23/5226

Abstract: An integrated circuit device includes a substrate having an active region, a conductive landing pad at a first vertical level above the substrate and connected to the active region, a capacitor including a lower electrode at a second vertical level higher than the first vertical level above the substrate, and a conductive multifunction plug including an extended landing pad portion at a third vertical level between the first vertical level and the second vertical level and contacting the conductive landing pad, and an extended lower electrode portion integrally connected to the extended landing pad portion and contacting the lower electrode. The capacitor further includes a dielectric layer covering a surface of the lower electrode and the extended lower electrode portion of the conductive multifunction plug.

公开(公告)号：US20230121734A1

公开(公告)日：2023-04-20

申请号：US17865497

申请日：2022-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Yu ,  Jieun Lee ,  Deoksung Hwang ,  Gisung Kim ,  Seungyoung Seo

IPC: H01L27/108

Abstract: A semiconductor device may include bit line structures on a substrate, a contact plug structure on the substrate between the bit line structures, and a capacitor electrically connected to the contact plug structure. The contact plug structure may include a first contact plug, a second contact plug, and a third contact plug sequentially stacked. An upper surface of the second contact plug includes an upper recess. The third contact plug may fill the upper recess, and may protrude above the upper recess. An upper surface of the third contact plug may be higher than a top surface of the bit line structures.