公开(公告)号：US12074738B2

公开(公告)日：2024-08-27

申请号：US17951482

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jahoon Jin ,  Kyunghwan Min ,  Soomin Lee ,  Sang-Ho Kim ,  Jihoon Lim ,  Sodam Ju ,  Hyun Su Chea

IPC: H04L25/03 ,  H04B1/16 ,  H04L1/20 ,  H04L7/00

CPC classification number: H04L25/03878 ,  H04B1/16 ,  H04L1/205 ,  H04L7/0079

Abstract: A semiconductor device including a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n−1 first signals having two signal levels. The device includes a jitter compensation circuit configured to receive the n−1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n−1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n−1 first signals transitions from the second signal level to the first signal level, to output n−1 second signals.

公开(公告)号：US11483000B2

公开(公告)日：2022-10-25

申请号：US17160888

申请日：2021-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwang Ho Choi ,  Yungeun Nam ,  Sodam Ju

IPC: H03K3/00 ,  H03K5/00 ,  H03K5/12 ,  H03K5/1252 ,  H03K19/0185 ,  G11C7/10 ,  G11C11/4093 ,  H04L25/02

Abstract: An interface circuit includes a first switch element connected to a first power supply node, supplying a first power supply voltage, and an output node, transmitting an output signal, and controlled by a first input signal, a second switch element connected to a second power supply node, supplying a second power supply voltage, lower than the first power supply voltage, and the output node and controlled by a second input signal, different from the first input signal, a first resistor connected between the first power supply node and the first switch element, a second resistor connected between the second power supply node and the second switch element, a first capacitor connected between the first resistor and the first switch element and charged and discharged by a first control signal, a second capacitor connected between the second resistor and the second switch element and charged and discharged by a second control signal, and a buffer circuit configured to output the first control signal and the second control signal and connected to a third power supply node, supplying a third power supply voltage, through a first variable resistor and connected to a fourth power supply node, supplying a fourth power supply voltage, lower than the third power supply node, through a second variable resistor.