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公开(公告)号：US12248018B2
公开(公告)日：2025-03-11
申请号：US18047366
申请日：2022-10-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeon Ho Jung , Jong Wook Kye , Min Woo Kwak , Mi Joung Kim , Chan Wook Park , Do Hoon Byun , Kwan Seong Lee , Jae Ho Lee , Jae Seung Choi , Hwang Ho Choi
Abstract: A semiconductor chip includes a semiconductor device connected between a first node to which a power supply voltage is applied and a second node to which a ground voltage is applied, a first ring oscillator connected to the first node through a first supply switch and the second node through a first ground switch and a second ring oscillator connected to the first node through a second supply switch and the second node through a second ground switch, wherein the first supply and ground switches are configured to operate in response to a first control signal, thereby operating the first ring oscillator, and the second supply and ground switches are configured to operate in response to a second control signal, thereby operating the second ring oscillator.
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公开(公告)号：US10476510B2
公开(公告)日：2019-11-12
申请号：US16025508
申请日：2018-07-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hwang Ho Choi
Abstract: A clock and data recovery device associated with a data receiving apparatus, the clock and data recovery device including an oscillator configured to generate a clock signal; and a regulator configured to supply current to the oscillator, the regulator including, a first current source configured to supply a first current to the oscillator, and a second current source configured to supply a second current to the oscillator such that the second current is supplied to the oscillator, after a period of time, to de-emphasize the first current, the period of time being based on the first current.
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公开(公告)号：US20230176112A1
公开(公告)日：2023-06-08
申请号：US18047366
申请日：2022-10-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeon Ho Jung , Jong Wook Kye , Min Woo Kwak , Mi Joung Kim , Chan Wook Park , Do Hoon Byun , Kwan Seong Lee , Jae Ho Lee , Jae Seung Choi , Hwang Ho Choi
CPC classification number: G01R31/2856 , H03K3/0315 , H03K3/011 , G01R31/3004
Abstract: A semiconductor chip includes a semiconductor device connected between a first node to which a power supply voltage is applied and a second node to which a ground voltage is applied, a first ring oscillator connected to the first node through a first supply switch and the second node through a first ground switch and a second ring oscillator connected to the first node through a second supply switch and the second node through a second ground switch, wherein the first supply and ground switches are configured to operate in response to a first control signal, thereby operating the first ring oscillator, and the second supply and ground switches are configured to operate in response to a second control signal, thereby operating the second ring oscillator.
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公开(公告)号：US11483000B2
公开(公告)日：2022-10-25
申请号：US17160888
申请日：2021-01-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hwang Ho Choi , Yungeun Nam , Sodam Ju
IPC: H03K3/00 , H03K5/00 , H03K5/12 , H03K5/1252 , H03K19/0185 , G11C7/10 , G11C11/4093 , H04L25/02
Abstract: An interface circuit includes a first switch element connected to a first power supply node, supplying a first power supply voltage, and an output node, transmitting an output signal, and controlled by a first input signal, a second switch element connected to a second power supply node, supplying a second power supply voltage, lower than the first power supply voltage, and the output node and controlled by a second input signal, different from the first input signal, a first resistor connected between the first power supply node and the first switch element, a second resistor connected between the second power supply node and the second switch element, a first capacitor connected between the first resistor and the first switch element and charged and discharged by a first control signal, a second capacitor connected between the second resistor and the second switch element and charged and discharged by a second control signal, and a buffer circuit configured to output the first control signal and the second control signal and connected to a third power supply node, supplying a third power supply voltage, through a first variable resistor and connected to a fourth power supply node, supplying a fourth power supply voltage, lower than the third power supply node, through a second variable resistor.
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