公开(公告)号：US20230301063A1

公开(公告)日：2023-09-21

申请号：US18094789

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soobin Yim ,  Insu Kim ,  Seohyun Maeng ,  Kijong Park ,  Imsoo Park ,  Kiseok Lee

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/05

Abstract: A semiconductor device may include first pillar insulation patterns on a substrate, second pillar insulation patterns on the substrate, silicon patterns stacked on the substrate to be spaced apart from each other in a vertical direction, a word line on each of upper and lower surfaces of each silicon pattern, a bit line contacting a first sidewall of at least a first silicon pattern of the silicon patterns, and a capacitor contacting a second sidewall of the first silicon pattern. Each of the first pillar insulation patterns may extend in the vertical direction from an upper surface of the substrate. The first pillar insulation patterns may be spaced apart from each other in a first direction, and may be aligned in a line. Each of the second pillar insulation patterns may extend in the vertical direction. The second pillar insulation patterns may be spaced apart from each other in the first direction, and may be aligned in a line. The second pillar insulation patterns and the first pillar insulation patterns may overlap with each other in a second direction perpendicular to the first direction. Each of the silicon patterns may extend in the second direction and be positioned between two first pillar insulation patterns and between two second pillar insulation patterns, and each of the silicon patterns may include two sidewalls opposite each other in the first direction and having a straight line shape. Each word line may extend in the first direction to cross the silicon patterns. Each word line may contact a sidewall of at least one insulation pattern of the first pillar insulation patterns and/or at least one insulation pattern of the second pillar insulation patterns. The bit line may extend in the vertical direction. The capacitor may be disposed in a horizontal direction to have a dielectric layer horizontally between a lower electrode and an upper electrode.

公开(公告)号：US20230178505A1

公开(公告)日：2023-06-08

申请号：US18050497

申请日：2022-10-28

Applicant: Samsung Electronics Co.. Ltd.

Inventor： KISEOK LEE ,  Hyungeun Choi ,  Gijae Kang ,  Keunnam Kim ,  Soobin Yim ,  Moonyoung Jeong ,  Seungjae Jung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H10B12/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/80 ,  H01L25/50 ,  H01L27/10805 ,  H01L27/10897 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Semiconductor memory devices may include a cell array structure that may include a memory cell array including three-dimensionally arranged memory cells and first bonding pads connected to the memory cell array and a peripheral circuit structure that may include peripheral circuits and second bonding pads bonded to the first bonding pads. The cell array structure may include a lower dielectric layer having a first surface and a second surface opposite to the first surface, a stack structure including horizontal electrodes stacked in a vertical direction on the first surface of the lower dielectric layer, a vertical structure including vertical conductive patterns that extend in the vertical direction and cross the horizontal electrodes, and an input/output pad on the second surface of the lower dielectric layer.