公开(公告)号：US20240145013A1

公开(公告)日：2024-05-02

申请号：US18367799

申请日：2023-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Insu Kim ,  Daeseok Byeon

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3459 ,  G11C16/32

Abstract: A memory device includes a memory cell array, and a page buffer circuit including a plurality of page buffers selectively connected to memory cells via a plurality of bit lines, each of the plurality of page buffers including a sensing node. The sensing nodes may be charged to different levels during verification of programming states of the memory cells. For example, a first sensing node of a first page buffer connected to a first memory cell targeted for programming to a first program state from among the plurality of page buffers is precharged to a first level in a first precharge period during verification of the first program state. A second sensing node of a second page buffer connected to a second memory cell targeted for programming to a second program state charged to a second level during verification of the second program state, wherein the second level is different from the first level.

公开(公告)号：US20240055055A1

公开(公告)日：2024-02-15

申请号：US18197258

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Insu Kim ,  Jaehue Shin

IPC: G11C16/24 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  H01L25/065 ,  H01L23/00 ,  H10B80/00

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  H01L25/0657 ,  H01L24/08 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected to the plurality of memory cells via a plurality of bit lines, and a plurality of cache latches respectively corresponding to the plurality of page buffer units. Each of the plurality of page buffer units includes a pass transistor that is connected to a corresponding sensing node and is driven according to a pass control signal, and the memory device is configured such that in a data sensing period, a sensing node of a selected page buffer unit among the plurality of page buffer units is actively connected to a sensing node of an unselected page buffer unit among the plurality of page buffer units.

公开(公告)号：US20230301063A1

公开(公告)日：2023-09-21

申请号：US18094789

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soobin Yim ,  Insu Kim ,  Seohyun Maeng ,  Kijong Park ,  Imsoo Park ,  Kiseok Lee

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/05

Abstract: A semiconductor device may include first pillar insulation patterns on a substrate, second pillar insulation patterns on the substrate, silicon patterns stacked on the substrate to be spaced apart from each other in a vertical direction, a word line on each of upper and lower surfaces of each silicon pattern, a bit line contacting a first sidewall of at least a first silicon pattern of the silicon patterns, and a capacitor contacting a second sidewall of the first silicon pattern. Each of the first pillar insulation patterns may extend in the vertical direction from an upper surface of the substrate. The first pillar insulation patterns may be spaced apart from each other in a first direction, and may be aligned in a line. Each of the second pillar insulation patterns may extend in the vertical direction. The second pillar insulation patterns may be spaced apart from each other in the first direction, and may be aligned in a line. The second pillar insulation patterns and the first pillar insulation patterns may overlap with each other in a second direction perpendicular to the first direction. Each of the silicon patterns may extend in the second direction and be positioned between two first pillar insulation patterns and between two second pillar insulation patterns, and each of the silicon patterns may include two sidewalls opposite each other in the first direction and having a straight line shape. Each word line may extend in the first direction to cross the silicon patterns. Each word line may contact a sidewall of at least one insulation pattern of the first pillar insulation patterns and/or at least one insulation pattern of the second pillar insulation patterns. The bit line may extend in the vertical direction. The capacitor may be disposed in a horizontal direction to have a dielectric layer horizontally between a lower electrode and an upper electrode.

公开(公告)号：US11388841B2

公开(公告)日：2022-07-12

申请号：US17266355

申请日：2019-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmin Oh ,  Sungjin Park ,  Daegyu Kang ,  Insu Kim ,  Daegi Lee ,  Jonghyun Lee

IPC: H05K7/20 ,  H04R1/02 ,  H04R9/02

Abstract: An electronic device according to various embodiments of the disclosure includes: a housing including a plurality of acoustic holes; an enclosure mounted in the housing; at least one heating element disposed in the enclosure; a heat dissipation structure disposed on the heating element to transfer heat generated from the heating element; and a heat dissipation duct disposed at least partially on the heat dissipation structure to provide a path for transferring the heat transferred from the heat dissipation structure to the outside through the acoustic holes. The heat dissipation structure may include: at least one first heat transfer member coupled to the one heating element; and a second heat transfer member disposed at least partially on the first heat transfer member to transfer, to the heat dissipation duct, heat transferred from the first heat transfer member.