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    Method and apparatus for plasma etching
    1.
    发明授权
    Method and apparatus for plasma etching 有权

    公开(公告)号：US10096453B2

    公开(公告)日：2018-10-09

    申请号：US15133989

    申请日：2016-04-20

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kijong Park ,  Jun-Youl Yang ,  Yongsun Ko ,  Kyunghyun Kim ,  Taeheon Kim ,  Jae Jin Shin

    IPC分类号： H01J37/32

    摘要： A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.

    Semiconductor devices
    4.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US10930654B2

    公开(公告)日：2021-02-23

    申请号：US16441100

    申请日：2019-06-14

    申请人： Samsung Electronics Co., Ltd.

    发明人： Hanjin Lim ,  Kijong Park ,  Younsoo Kim

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L49/02

    摘要： Semiconductor devices are provided. The semiconductor devices may include an active pattern on a substrate. The active pattern may include a first source/drain region and a second source/drain region. The semiconductor devices may also include a bit line electrically connected to the first source/drain region, a first connection electrode electrically connected to the second source/drain region, and a capacitor on the first connection electrode. The capacitor may include a first electrode, a second electrode, and a dielectric pattern between the first and second electrodes. A lower portion of the dielectric pattern may overlap a top surface of the first connection electrode, and the first electrode may extend on an upper portion of a sidewall of the first connection electrode.

    SEMICONDUCTOR PACKAGES HAVING CONNECTING STRUCTURE
    5.
    发明申请
    SEMICONDUCTOR PACKAGES HAVING CONNECTING STRUCTURE 有权

    公开(公告)号：US20230014933A1

    公开(公告)日：2023-01-19

    申请号：US17679507

    申请日：2022-02-24

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kijong Park

    IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H01L23/498

    摘要： A semiconductor package includes a substrate including an upper pad at a top surface of the substrate, a semiconductor chip on the substrate and including a chip pad at a top surface of the semiconductor chip, a connecting structure on the semiconductor chip and including a connecting pad at a top surface of the connecting structure and electrically connected to the upper pad, an encapsulant covering the substrate, the semiconductor chip, and the connecting structure, and a test terminal on the connecting structure and extending through the encapsulant. The connecting structure electrically interconnects the semiconductor chip and the test terminal.

    Method and apparatus for plasma etching
    6.
    发明授权
    Method and apparatus for plasma etching 有权

    公开(公告)号：US10580617B2

    公开(公告)日：2020-03-03

    申请号：US15841230

    申请日：2017-12-13

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kijong Park ,  Jun-Youl Yang ,  Yongsun Ko ,  Kyunghyun Kim ,  Taeheon Kim ,  Jae Jin Shin

    IPC分类号： H01J37/32

    摘要： A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.

    SEMICONDUCTOR DEVICES
    8.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230301063A1

    公开(公告)日：2023-09-21

    申请号：US18094789

    申请日：2023-01-09

    申请人： Samsung Electronics Co., Ltd.

    发明人： Soobin Yim ,  Insu Kim ,  Seohyun Maeng ,  Kijong Park ,  Imsoo Park ,  Kiseok Lee

    IPC分类号： H10B12/00

    CPC分类号： H10B12/30 ,  H10B12/05

    摘要： A semiconductor device may include first pillar insulation patterns on a substrate, second pillar insulation patterns on the substrate, silicon patterns stacked on the substrate to be spaced apart from each other in a vertical direction, a word line on each of upper and lower surfaces of each silicon pattern, a bit line contacting a first sidewall of at least a first silicon pattern of the silicon patterns, and a capacitor contacting a second sidewall of the first silicon pattern. Each of the first pillar insulation patterns may extend in the vertical direction from an upper surface of the substrate. The first pillar insulation patterns may be spaced apart from each other in a first direction, and may be aligned in a line. Each of the second pillar insulation patterns may extend in the vertical direction. The second pillar insulation patterns may be spaced apart from each other in the first direction, and may be aligned in a line. The second pillar insulation patterns and the first pillar insulation patterns may overlap with each other in a second direction perpendicular to the first direction. Each of the silicon patterns may extend in the second direction and be positioned between two first pillar insulation patterns and between two second pillar insulation patterns, and each of the silicon patterns may include two sidewalls opposite each other in the first direction and having a straight line shape. Each word line may extend in the first direction to cross the silicon patterns. Each word line may contact a sidewall of at least one insulation pattern of the first pillar insulation patterns and/or at least one insulation pattern of the second pillar insulation patterns. The bit line may extend in the vertical direction. The capacitor may be disposed in a horizontal direction to have a dielectric layer horizontally between a lower electrode and an upper electrode.