-
公开(公告)号：US10649849B2
公开(公告)日：2020-05-12
申请号：US15938092
申请日：2018-03-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Hun Kim , Su-Yeon Doo , Dong-Seok Kang , Hye-Jung Kwon , Young-Ju Kim
Abstract: A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.
-
Patent Agency Ranking
2.发明授权公开(公告)号：US09767050B2
公开(公告)日：2017-09-19
申请号：US15065211
申请日：2016-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Su-Yeon Doo , Tae-Young Oh , Kwang-Il Park
IPC: G11C7/00 , G06F13/16 , G11C11/406
CPC classification number: G06F13/1636 , G11C11/40603 , G11C11/40611 , G11C11/40615
Abstract: A memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a plurality of dynamic memory cells. The memory controller controls the semiconductor memory device. The memory controller applies an auto-refresh command to the semiconductor memory device at each refresh interval of the semiconductor memory device such that the semiconductor memory performs a refresh operation in a normal mode, and does not apply the auto-refresh command to the semiconductor memory device during a self-refresh interval in which the semiconductor memory performs a self-refresh operation. After the semiconductor memory device exits from the self-refresh interval, the memory controller adjusts an application of the auto-refresh command in the normal mode by reflecting information of the self-refresh interval.
-
公开(公告)号：US11438016B2
公开(公告)日：2022-09-06
申请号：US17110777
申请日：2020-12-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Uhn Cha , Ye-Sin Ryu , Young-Sik Kim , Su-Yeon Doo
Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
-
公开(公告)号：US11223373B2
公开(公告)日：2022-01-11
申请号：US16599648
申请日：2019-10-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Uhn Cha , Ye-Sin Ryu , Young-Sik Kim , Su-Yeon Doo
Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
-
公开(公告)号：US10476529B2
公开(公告)日：2019-11-12
申请号：US15789653
申请日：2017-10-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Uhn Cha , Ye-Sin Ryu , Young-Sik Kim , Su-Yeon Doo
Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
-
公开(公告)号：US20180159558A1
公开(公告)日：2018-06-07
申请号：US15789653
申请日：2017-10-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Uhn Cha , Ye-Sin Ryu , Young-Sik Kim , Su-Yeon Doo
CPC classification number: H03M13/2906 , H03M13/09
Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
-
-
-
-
-
Search Results
6
records
(took 0.013 seconds)
