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    Semiconductor memory devices and memory systems including the same
    1.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权

    公开(公告)号：US10191805B2

    公开(公告)日：2019-01-29

    申请号：US15204536

    申请日：2016-07-07

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sang-Uhn Cha ,  Hoi-Ju Chung

    IPC分类号： G06F11/10 ,  G11C29/52 ,  G11C29/04

    摘要： A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit performs an error correction code (ECC) encoding on write data to be stored in the memory cell array, and performs an ECC decoding on read data from the memory cell array. The control logic circuit controls access to the memory cell array and generates an engine configuration selection signal based on a command. The error correction circuit reconfigures a number of units for which ECC including the ECC encoding and the ECC decoding is performed, in response to the engine configuration selection signal.

    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices
    3.
    发明授权
    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11557332B2

    公开(公告)日：2023-01-17

    申请号：US17322227

    申请日：2021-05-17

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

    IPC分类号： G11C7/00 ,  G11C11/406 ,  G06F11/10

    摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices
    4.
    发明授权
    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11385960B2

    公开(公告)日：2022-07-12

    申请号：US16894354

    申请日：2020-06-05

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sang-Uhn Cha

    IPC分类号： G06F11/10 ,  H03M13/15

    摘要： A semiconductor memory device is provided. The device includes a memory cell array including a plurality of dynamic memory cells; an error correction code (ECC) engine; an input/output (I/O) gating circuit connected between the ECC engine and the memory cell array; an error information register configured to store an error address and a first syndrome, the error address and the first syndrome being associated with a first error bit in a first codeword stored in a first page of the memory cell array; and a control logic configured to, based on the first codeword being read again and including a second error bit which is different from the first error bit, recover a second syndrome associated with the second error bit by using the first syndrome stored in the error information register and sequentially correct the first error bit and the second error bit.