公开(公告)号：US20150243345A1

公开(公告)日：2015-08-27

申请号：US14517255

申请日：2014-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua KIM ,  Chul-Woo PARK

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/4082 ,  G11C5/04 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory module may include m memory devices. Each of the m memory devices may be divided into n regions each region including a plurality of rows corresponding to row addresses, where m and n are integers equal to or greater than 2. An address detector included in each of the m memory devices, wherein for each of the address detectors, the address detector may be configured to count a number of accesses to a particular row address included in one region of each of the m memory devices during a predetermined time period, and be configured to output a detect signal when the number of the counted accesses reaches a reference value. Each of the max-count address generators may be configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other max-count address generators count accesses.

Abstract translation: 存储器模块可以包括m个存储器件。 每个m个存储器件可以被划分为n个区域，每个区域包括对应于行地址的多个行，其中m和n是等于或大于2的整数。一种地址检测器，包括在每个m个存储器件中，其中 对于每个地址检测器，地址检测器可以被配置为在预定时间段内对包括在每个m个存储器件的一个区域中的特定行地址的访问次数进行计数，并且被配置为当 计数访问次数达到参考值。 每个最大计数地址生成器可以被配置为对与其他最大计数地址生成器计数访问的行地址集合不同的一组行地址来计数访问次数。

公开(公告)号：US20150155055A1

公开(公告)日：2015-06-04

申请号：US14462843

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua KIM ,  Dongsoo KANG ,  Chulwoo PARK ,  Jun Hee YOO ,  Hak-Soo YU ,  Jaeyoun YOUN ,  Sung Hyun LEE ,  Jinsu JUNG ,  Hyojin CHOI

IPC: G11C29/04 ,  G11C17/16

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/4402

Abstract: A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.

Abstract translation: 包括存储单元阵列和反熔丝阵列的半导体存储器件的测试方法包括检测包括在存储单元阵列中的故障单元; 确定与检测到的故障小区相对应的故障地址; 将所确定的故障地址存储在所述存储单元阵列的第一区域中; 并读取存储在第一区域中的故障地址，以对反熔丝阵列中的读故障地址进行编程。 根据半导体存储器件和半导体存储器系统的测试方法，由于可以在没有用于存储地址的附加存储器的情况下执行测试操作，所以半导体存储器件和测试电路可以被小面积体现。