公开(公告)号：US20230409902A1

公开(公告)日：2023-12-21

申请号：US18113794

申请日：2023-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhwi PARK ,  Hyojin CHOI

IPC: G06N3/08 ,  G06N3/0475

CPC classification number: G06N3/08 ,  G06N3/0475

Abstract: An operating method of an electronic device is disclosed. The operating method includes generating an input tensor by using a generator network, obtaining a first score by inputting the input tensor to a target row refresh logic module, storing a pair of the generator network and the first score in an evolution pool when the first score is greater than a threshold value, training a critic network based on the input tensor and the first score when the number of times of iteration is smaller than the maximum number of times of iteration, and training the generator network based on a training result of the critic network when the number of times of iteration is smaller than the maximum number of times of iteration.

公开(公告)号：US20220084564A1

公开(公告)日：2022-03-17

申请号：US17340423

申请日：2021-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin CHOI ,  Jaewon KO ,  Hyeongtae KIM ,  Younsik PARK ,  Hyeonsik SON

IPC: G11C7/10 ,  G11C11/408 ,  G11C29/00

Abstract: A memory device including: a memory cell array including a plurality of memory cell rows; an address buffer configured to store addresses of target rows of the plurality of memory cell rows, wherein the addresses of the target rows have been repeatedly accessed; a minimum access output circuit configured to select, when there are a plurality of rows having a same minimum access count among the target rows, any one of the plurality of rows having the same minimum access count as a minimum access row based on a selection command value, and to output an index value of the minimum access row; and a control circuit configured to output a command instructing replacement of an address corresponding to the index value of the minimum access row with an address of an access row and storage of the address of the access row in the address buffer.

公开(公告)号：US20150155055A1

公开(公告)日：2015-06-04

申请号：US14462843

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua KIM ,  Dongsoo KANG ,  Chulwoo PARK ,  Jun Hee YOO ,  Hak-Soo YU ,  Jaeyoun YOUN ,  Sung Hyun LEE ,  Jinsu JUNG ,  Hyojin CHOI

IPC: G11C29/04 ,  G11C17/16

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/4402

Abstract: A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.

Abstract translation: 包括存储单元阵列和反熔丝阵列的半导体存储器件的测试方法包括检测包括在存储单元阵列中的故障单元; 确定与检测到的故障小区相对应的故障地址; 将所确定的故障地址存储在所述存储单元阵列的第一区域中; 并读取存储在第一区域中的故障地址，以对反熔丝阵列中的读故障地址进行编程。 根据半导体存储器件和半导体存储器系统的测试方法，由于可以在没有用于存储地址的附加存储器的情况下执行测试操作，所以半导体存储器件和测试电路可以被小面积体现。

公开(公告)号：US20140025880A1

公开(公告)日：2014-01-23

申请号：US13943790

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haksoo YU ,  Dae-Hyun KIM ,  Uksong KANG ,  Chulwoo PARK ,  Joosun CHOI ,  Hyojin CHOI

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0638 ,  G11C11/005 ,  G11C11/403 ,  G11C11/40622 ,  G11C29/783 ,  G11C2029/4402

Abstract: A semiconductor memory cell array is provided which includes a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed different from the first operating speed. The first and second memory cell array areas are accessed by addressing of a DRAM controller.

Abstract translation: 提供一种半导体存储单元阵列，其包括第一存储单元阵列区域，该第一存储单元阵列区域包括布置在具有第一运行速度的矩阵中的芯片中的第一组存储单元; 以及第二存储单元阵列区域，包括布置在所述芯片中的行和列的矩阵并具有与所述第一操作速度不同的第二操作速度的第二组存储单元。 通过DRAM控制器的寻址来访问第一和第二存储单元阵列区域。