公开(公告)号：US20230269205A1

公开(公告)日：2023-08-24

申请号：US18311181

申请日：2023-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongmin JO ,  Heeseong LEE ,  Jaehyun KIM ,  Jinsu JUNG

IPC: H04L49/90 ,  H04L49/00 ,  H04L49/109

CPC classification number: H04L49/9094 ,  H04L49/3027 ,  H04L49/9021 ,  H04L49/109

Abstract: A Network-on-Chip (NoC) includes a packet transmission switch, and a corresponding method of operating the NoC includes storing packets received from an input terminal in a buffer, storing buffer locations in which each of the packets is stored in an ordering queue of an output terminal, and sequentially outputting the packets from the output terminal according to the buffer locations.

公开(公告)号：US20150155055A1

公开(公告)日：2015-06-04

申请号：US14462843

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua KIM ,  Dongsoo KANG ,  Chulwoo PARK ,  Jun Hee YOO ,  Hak-Soo YU ,  Jaeyoun YOUN ,  Sung Hyun LEE ,  Jinsu JUNG ,  Hyojin CHOI

IPC: G11C29/04 ,  G11C17/16

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/4402

Abstract: A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.

Abstract translation: 包括存储单元阵列和反熔丝阵列的半导体存储器件的测试方法包括检测包括在存储单元阵列中的故障单元; 确定与检测到的故障小区相对应的故障地址; 将所确定的故障地址存储在所述存储单元阵列的第一区域中; 并读取存储在第一区域中的故障地址，以对反熔丝阵列中的读故障地址进行编程。 根据半导体存储器件和半导体存储器系统的测试方法，由于可以在没有用于存储地址的附加存储器的情况下执行测试操作，所以半导体存储器件和测试电路可以被小面积体现。