公开(公告)号：US20150227481A1

公开(公告)日：2015-08-13

申请号：US14616845

申请日：2015-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hee YOO ,  Jaegeun YUN ,  Bub-chul JEONG ,  Dongsoo KANG

IPC: G06F13/364 ,  G06F13/16

CPC classification number: G06F13/364 ,  G06F13/1673 ,  G06F13/4217 ,  G06F21/42 ,  G06F2221/2101

Abstract: A system interconnect is provided which includes a first channel configured to transmit a plurality of control signals based on a first clock, and a second channel configured to transmit a plurality of data signals which correspond to the control signals based on a second clock. The first channel and the second channel allows a predetermined range of out-of-orderness, and the predetermined range of the out-of-orderness indicates that an order of the control signals is different from an order of the data signals which correspond to the control signals.

Abstract translation: 提供了一种系统互连，其包括被配置为基于第一时钟发送多个控制信号的第一信道和被配置为基于第二时钟发送对应于控制信号的多个数据信号的第二信道。 第一通道和第二通道允许非正常的预定范围，并且失调的预定范围表示控制信号的顺序与数据信号的顺序不同，数据信号对应于 控制信号。

公开(公告)号：US20150155055A1

公开(公告)日：2015-06-04

申请号：US14462843

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua KIM ,  Dongsoo KANG ,  Chulwoo PARK ,  Jun Hee YOO ,  Hak-Soo YU ,  Jaeyoun YOUN ,  Sung Hyun LEE ,  Jinsu JUNG ,  Hyojin CHOI

IPC: G11C29/04 ,  G11C17/16

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/4402

Abstract: A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.

Abstract translation: 包括存储单元阵列和反熔丝阵列的半导体存储器件的测试方法包括检测包括在存储单元阵列中的故障单元; 确定与检测到的故障小区相对应的故障地址; 将所确定的故障地址存储在所述存储单元阵列的第一区域中; 并读取存储在第一区域中的故障地址，以对反熔丝阵列中的读故障地址进行编程。 根据半导体存储器件和半导体存储器系统的测试方法，由于可以在没有用于存储地址的附加存储器的情况下执行测试操作，所以半导体存储器件和测试电路可以被小面积体现。